• 4325 Citations
  • 35 h-Index
1991 …2018
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  • 6 Similar Profiles
Decoding Engineering & Materials Science
Magnetic recording Engineering & Materials Science
Optical communication Engineering & Materials Science
Error correction Engineering & Materials Science
Light transmission Engineering & Materials Science
Iterative decoding Engineering & Materials Science
parity Physics & Astronomy
coding Physics & Astronomy

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Research Output 1991 2018

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

Le, K., Ghaffari, F., Kessal, L., Declercq, D., Boutillon, E., Winstead, C. & Vasic, B., Jul 4 2018, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.

Research output: Contribution to journalArticle

Error correction
Decoding
Hardware
Application specific integrated circuits
Throughput

Efficient FPGA implementation of probabilistic gallager B LDPC decoder

Ghaffari, F., Unal, B., Akoglu, A., Le, K., Declercq, D. & Vasic, B., Feb 14 2018, ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January, p. 178-181 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
Field programmable gate arrays (FPGA)
Message passing
Throughput
Monte Carlo simulation

Generic architectures for uniformly reweighted APP decoders

Ilic, V., Dupraz, E. & Vasic, B., Jan 3 2018, 2017 13th International Conference on Advanced Technologies, Systems and Services in Telecommunications, TELSIKS 2017 - Proceeding. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January, p. 308-316 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Throughput
Data storage equipment
Bit error rate
Computer hardware

Hard-decision decoding of LDPC codes under timing errors: Overview and new results

Brkic, S., Ivanis, P. & Vasić, B., Jan 5 2018, 2017 25th Telecommunications Forum, TELFOR 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-January, p. 1-8 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
Memory architecture
Logic gates
Error correction
Hardware

Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders

Unal, B., Akoglu, A., Ghaffari, F. & Vasić, B., Sep 1 2018, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 65, 9, p. 3074-3084 11 p., 8329987

Research output: Contribution to journalArticle

Error correction
Hardware
Decoding
Throughput
Field programmable gate arrays (FPGA)