• 4256 Citations
  • 35 h-Index
1991 …2018
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Research Output 1991 2018

2018

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

Le, K., Ghaffari, F., Kessal, L., Declercq, D., Boutillon, E., Winstead, C. & Vasic, B. Jul 4 2018 (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.

Research output: Contribution to journalArticle

Error correction
Decoding
Hardware
Application specific integrated circuits
Throughput

Efficient FPGA implementation of probabilistic gallager B LDPC decoder

Ghaffari, F., Unal, B., Akoglu, A., Le, K., Declercq, D. & Vasic, B. Feb 14 2018 ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January, p. 178-181 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
Field programmable gate arrays (FPGA)
Message passing
Throughput
Monte Carlo simulation

Generic architectures for uniformly reweighted APP decoders

Ilic, V., Dupraz, E. & Vasic, B. Jan 3 2018 2017 13th International Conference on Advanced Technologies, Systems and Services in Telecommunications, TELSIKS 2017 - Proceeding. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January, p. 308-316 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Throughput
Data storage equipment
Bit error rate
Computer hardware

Hard-decision decoding of LDPC codes under timing errors: Overview and new results

Brkic, S., Ivanis, P. & Vasić, B. Jan 5 2018 2017 25th Telecommunications Forum, TELFOR 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-January, p. 1-8 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
Memory architecture
Logic gates
Error correction
Hardware

Serial concatenation of reed muller and LDPC codes with low error floor

Xiao, X., Nasseri, M., Vasic, B. & Lin, S. Jan 17 2018 55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January, p. 688-693 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low-density Parity-check (LDPC) Codes
Concatenation
Decoding
Galois field
Trapping

Signal Processing and Coding Techniques for 2-D Magnetic Recording: An Overview

Garani, S. S., Dolecek, L., Barry, J., Sala, F. & Vasic, B. Feb 1 2018 In : Proceedings of the IEEE. 106, 2, p. 286-318 33 p., 8290590

Research output: Contribution to journalReview article

Magnetic recording
Signal processing
Intersymbol interference
Electronic equipment
Timing jitter

Stochastic resonance in iterative decoding: Message passing and gradient descent bit flipping

Ivanis, P., Brkic, S. & Vasic, B. Jan 3 2018 2017 13th International Conference on Advanced Technologies, Systems and Services in Telecommunications, TELSIKS 2017 - Proceeding. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January, p. 300-307 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Iterative decoding
Message passing
Logic gates
Decoding
Cryptography

Towards the exact rate-memory trade-off for uncoded caching with secure delivery

Bahrami, M., Attia, M. A., Tandon, R. & Vasić, B. Jan 17 2018 55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January, p. 878-885 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Caching
Servers
Trade-offs
Data storage equipment
Server
2017

2D LDPC Codes and Joint Detection and Decoding for Two-Dimensional Magnetic Recording

Matcha, C. K., Roy, S., Bahrami, M., Vasic, B. & Srinivasa, S. G. Aug 9 2017 (Accepted/In press) In : IEEE Transactions on Magnetics.

Research output: Contribution to journalArticle

Magnetic recording
Decoding
Synchronization
Engines
Signal detection
1 Citations

Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder

Unal, B., Ghaffari, F., Akoglu, A., Declercq, D. & Vasic, B. Aug 11 2017 Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017. Institute of Electrical and Electronics Engineers Inc., p. 333-336 4 p. 8010173

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
Error correction
Field programmable gate arrays (FPGA)
Communication systems
Throughput
1 Citations

A novel high-throughput, low-complexity bit-flipping decoder for LDPC codes

Le, K., Ghaffari, F., Declercq, D., Vasic, B. & Winstead, C. Dec 5 2017 Proceedings of the 2017 International Conference on Advanced Technologies for Communications, ATC 2017. IEEE Computer Society, Vol. 2017-October, p. 126-131 6 p. 8167601

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Throughput
Decoding
Signal generators
Error correction
Field programmable gate arrays (FPGA)
6 Citations

Approaching maximum likelihood performance of LDPC codes by stochastic resonance in noisy iterative decoders

Vasić, B., Ivaniš, P., Declercq, D. & LeTrung, K. Mar 27 2017 2016 Information Theory and Applications Workshop, ITA 2016. Institute of Electrical and Electronics Engineers Inc., 7888185

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Maximum likelihood
Hardware
Nails
Logic gates
Error correction
2 Citations

Asymptotic error probability of the Gallager B decoder under timing errors

Dupraz, E., Declercq, D. & Vasic, B. Apr 1 2017 In : IEEE Communications Letters. 21, 4, p. 698-701 4 p., 7805222

Research output: Contribution to journalArticle

Error Probability
Timing
Logic gates
Logic
Timing circuits
6 Citations

Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping

Le, K., Ghaffari, F., Declercq, D. & Vasic, B. Apr 1 2017 In : IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 4, p. 906-917 12 p., 7786873

Research output: Contribution to journalArticle

Hardware
Decoding
Error correction

Generalized belief propagation based deliberate bit flipping modulation coding

Bahrami, M. & Vasic, B. Feb 2 2017 2016 IEEE Global Communications Conference, GLOBECOM 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7841858

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Modulation
Magnetic recording
Error correction

Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders

Le, K., Ghaffari, F., Declercq, D. & Vasic, B. Sep 25 2017 IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050695

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Decoding
Error correction
Application specific integrated circuits
Statistical methods
1 Citations

Majority Logic Decoding under Data-Dependent Logic Gate Failures

Brkic, S., Ivaniš, P. & Vasić, B. Oct 1 2017 In : IEEE Transactions on Information Theory. 63, 10, p. 6295-6306 12 p., 8013135

Research output: Contribution to journalArticle

Majority logic
Logic gates
Decoding
Bit error rate
mathematics

Message-aggregation enhanced iterative hard-decision decoders

Brkic, S., Ivanis, P., Vasić, B. & Declercq, D. Mar 27 2017 2016 Information Theory and Applications Workshop, ITA 2016. Institute of Electrical and Electronics Engineers Inc., 7888184

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Agglomeration
Iterative decoding
Decoding

Multi-bit bit-flipping algorithm for column weight-4 LDPC codes

Xiao, X., Vasić, B. & Lin, S. Jan 1 2017 In : Proceedings of the International Telemetering Conference.

Research output: Contribution to journalConference article

parity
decoding
Decoding
bit error rate
Bit error rate
2 Citations

Multi-bit flipping algorithms with probabilistic gradient descent

Vasic, B., Ivanis, P. & Brkic, S. Aug 30 2017 2017 Information Theory and Applications Workshop, ITA 2017. Institute of Electrical and Electronics Engineers Inc., 8023480

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Boolean functions
Throughput

Multi-mode low-latency software-defined error correction for data centers

Ghaffari, F., Akoglu, A., Vasić, B. & Declercq, D. Sep 14 2017 2017 26th International Conference on Computer Communications and Networks, ICCCN 2017. Institute of Electrical and Electronics Engineers Inc., 8038467

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data Center
Error correction
Error Correction
Flash Memory
Flash memory

Performance of taylor-kuznetsov memories under timing errors

Dupraz, E., Vasic, B. & Declercq, D. Jul 28 2017 2017 IEEE International Conference on Communications, ICC 2017. Institute of Electrical and Electronics Engineers Inc., 7996548

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Memory architecture
Networks (circuits)

Stochastic resonance decoding for quantum LDPC codes

Raveendran, N., Nadkarni, P. J., Garani, S. S. & Vasic, B. Jul 28 2017 2017 IEEE International Conference on Communications, ICC 2017. Institute of Electrical and Electronics Engineers Inc., 7996747

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Error correction
Decoding
Iterative decoding
Logic gates
Networks (circuits)
2016

Check-hybrid GLDPC codes: Systematic elimination of trapping sets and guaranteed error correction capability

Ravanmehr, V., Khatami, M., Declercq, D. & Vasic, B. Dec 1 2016 In : Transactions on Emerging Telecommunications Technologies. 27, 12, p. 1679-1692 14 p.

Research output: Contribution to journalArticle

Error correction
Decoding
7 Citations

Error Errore Eicitur: A Stochastic Resonance Paradigm for Reliable Storage of Information on Unreliable Media

Ivanis, P. & Vasic, B. Sep 1 2016 In : IEEE Transactions on Communications. 64, 9, p. 3596-3608 13 p., 7509624

Research output: Contribution to journalArticle

Logic gates
Networks (circuits)
Data storage equipment
Iterative decoding
Nails
5 Citations

Generalized belief propagation based TDMR detector and decoder

Matcha, C. K., Bahrami, M., Roy, S., Srinivasa, S. G. & Vasic, B. Aug 10 2016 Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-August, p. 210-214 5 p. 7541291

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Belief Propagation
Magnetic recording
Detector
Detectors
Intersymbol Interference
3 Citations

Guaranteed error correction of faulty bit-flipping decoders under data-dependent gate failures

Brkic, S., Ivanis, P. & Vasic, B. Aug 10 2016 Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-August, p. 1561-1565 5 p. 7541561

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low-density Parity-check (LDPC) Codes
Dependent Data
Error correction
Error Correction
Expander

Guest Editorial Channel Modeling, Coding and Signal Processing for Novel Physical Memory Devices and Systems

Garani, S. S., Zhang, T., Motwani, R. H., Pozidis, H. & Vasic, B. Sep 1 2016 In : IEEE Journal on Selected Areas in Communications. 34, 9, p. 2289-2293 5 p., 7587447

Research output: Contribution to journalReview article

Signal processing
Data storage equipment
Energy efficiency
3 Citations

Improved PEG construction of large girth QC-LDPC codes

Diouf, M., Declercq, D., Fossorier, M., Ouya, S. & Vasic, B. Oct 17 2016 2016 9th International Symposium on Turbo Codes and Iterative Information Processing: Paths to 5G and Beyond, ISTC 2016. IEEE Computer Society, Vol. 2016-October, p. 146-150 5 p. 7593094

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Quasi-cyclic Codes
Low-density Parity-check (LDPC) Codes
Girth
Polyethylene glycols
Cycle
5 Citations

Information rates of constrained TDMR channels using generalized belief propagation

Khatami, M., Bahrami, M. & Vasic, B. Feb 23 2016 2015 IEEE Global Communications Conference, GLOBECOM 2015. Institute of Electrical and Electronics Engineers Inc., 7417728

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Magnetic recording
recording
Bit error rate
Channel capacity
coding
3 Citations

Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding

Declercq, D., Winstead, C., Vasic, B., Ghaffari, F., Ivanis, P. & Boutillon, E. Oct 17 2016 2016 9th International Symposium on Turbo Codes and Iterative Information Processing: Paths to 5G and Beyond, ISTC 2016. IEEE Computer Society, Vol. 2016-October, p. 300-304 5 p. 7593125

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gradient Descent
Trapping
Maximum likelihood
Maximum Likelihood
Decoding

Noise predictive information rate estimation for TDMR channels

Bahrami, M. & Vasić, B. 2016 In : Proceedings of the International Telemetering Conference. 52, p. 421-427 7 p.

Research output: Contribution to journalArticle

Magnetic recording
magnetic recording
recording
Jitter
irregularities
4 Citations

Optimization of Bit Geometry and Multi-Reader Geometry for Two-Dimensional Magnetic Recording

Barry, J. R., Vasic, B., Khatami, M., Bahrami, M., Nakamura, Y., Okamoto, Y. & Kanai, Y. Feb 1 2016 In : IEEE Transactions on Magnetics. 52, 2, 7283623

Research output: Contribution to journalArticle

Magnetic recording
Aspect ratio
Geometry
Signal detection
Full width at half maximum
2 Citations

Performance evaluation of faulty iterative decoders using absorbing Markov chains

Ivanis, P., Vasic, B. & Declercq, D. Aug 10 2016 Proceedings - ISIT 2016; 2016 IEEE International Symposium on Information Theory. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-August, p. 1566-1570 5 p. 7541562

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Logic gates
Absorbing
Markov processes
Performance Evaluation
Markov chain
2015
12 Citations

Analysis and Design of Finite Alphabet Iterative Decoders Robust to Faulty Hardware

Dupraz, E., Declercq, D., Vasic, B. & Savin, V. Aug 1 2015 In : IEEE Transactions on Communications. 63, 8, p. 2797-2809 13 p., 7147804

Research output: Contribution to journalArticle

Hardware
Message passing
Monte Carlo simulation
2 Citations

Analysis of Taylor-Kuznetsov memory using one-step majority logic decoder

Dupraz, E., Declercq, D. & Vasić, B. Oct 27 2015 2015 Information Theory and Applications Workshop, ITA 2015 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 46-53 8 p. 7308965

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Majority logic
Data storage equipment
Degradation
6 Citations

A PEG-like LDPC code design avoiding short trapping sets

Diouf, M., Declercq, D., Ouya, S. & Vasic, B. Sep 28 2015 IEEE International Symposium on Information Theory - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-June, p. 1079-1083 5 p. 7282621

Research output: Chapter in Book/Report/Conference proceedingConference contribution

LDPC Codes
Trapping
Girth
Cost functions
Quasi-cyclic Codes
10 Citations

A Study of TDMR signal processing opportunities based on quasi-micromagnetic simulations

Vasic, B., Khatami, M., Nakamura, Y., Okamoto, Y., Kanai, Y., Barry, J. R., McLaughlin, S. W. & Sadeghian, E. B. Apr 1 2015 In : IEEE Transactions on Magnetics. 51, 4, 7109973

Research output: Contribution to journalArticle

Magnetostatics
Magnetic recording
Exchange interactions
Signal processing

Decoder diversity architectures for finite alphabet iterative decoders

Vasić, B., Declercq, D. & Planjery, S. K. Apr 24 2015 Conference Record - Asilomar Conference on Signals, Systems and Computers. IEEE Computer Society, Vol. 2015-April, p. 131-135 5 p. 7094412

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
8 Citations

Efficient realization of probabilistic gradient descent bit flipping decoders

Le, K., Declercq, D., Ghaffari, F., Spagnol, C., Popovici, E., Ivanis, P. & Vasic, B. Jul 27 2015 Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-July, p. 1494-1497 4 p. 7168928

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Error correction
Hardware
Binary sequences
10 Citations

Fault-resilient decoders and memories made of unreliable components

Vasić, B., Ivanis, P., Brkic, S. & Ravanmehr, V. Oct 27 2015 2015 Information Theory and Applications Workshop, ITA 2015 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 136-142 7 p. 7308978

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Iterative decoding
Hardware
Data storage equipment
Logic gates
Free energy
7 Citations

Investigation into Harmful Patterns over Multitrack Shingled Magnetic Detection Using the Voronoi Model

Bahrami, M., Matcha, C. K., Khatami, S. M., Roy, S., Srinivasa, S. G. & Vasic, B. Dec 1 2015 In : IEEE Transactions on Magnetics. 51, 12, 7165654

Research output: Contribution to journalArticle

Magnetic recording
Intersymbol interference
Signal detection
Magnetic storage
Detectors
4 Citations

Low complexity memory architectures based on LDPC codes: Benefits and disadvantages

Vasić, B., Ivaniš, P. & Brkic, S. Dec 14 2015 2015 12th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services, TELSIKS 2015. Institute of Electrical and Electronics Engineers Inc., p. 11-18 8 p. 7357727

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Memory architecture
Data storage equipment
Error correction
9 Citations

MUDRI: A fault-tolerant decoding algorithm

Ivanis, P., Al Rasheed, O. & Vasic, B. Sep 9 2015 IEEE International Conference on Communications. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-September, p. 4291-4296 6 p. 7248997

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decoding
Hardware
Logic gates
14 Citations

On Fault Tolerance of the Gallager B Decoder under Data-Dependent Gate Failures

Brkic, S., Al Rasheed, O., Ivanis, P. & Vasic, B. Aug 1 2015 In : IEEE Communications Letters. 19, 8, p. 1299-1302 4 p., 7120101

Research output: Contribution to journalArticle

Dependent Data
Fault tolerance
Fault Tolerance
Hardware
Degradation
7 Citations

Reliability of memories built from unreliable components under data-dependent gate failures

Brkic, S., Ivaniš, P. & Vasić, B. Dec 1 2015 In : IEEE Communications Letters. 19, 12, p. 2098-2101 4 p., 7312924

Research output: Contribution to journalArticle

Dependent Data
Data storage equipment
Memory architecture
Logic gates
Fault tolerance
6 Citations

Symmetric information rate estimation and bit aspect ratio optimization for TDMR using Generalized Belief Propagation

Khatami, M., Bahrami, M. & Vasic, B. Sep 28 2015 IEEE International Symposium on Information Theory - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-June, p. 1620-1624 5 p. 7282730

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Information Rates
Belief Propagation
Magnetic recording
Aspect Ratio
Aspect ratio
2 Citations

Viterbi Detection for Compressively Sampled FHSS-GFSK Signals

Pan, L., Marcellin, M. W., Ryan, W. E. & Vasic, B. Nov 15 2015 In : IEEE Transactions on Signal Processing. 63, 22, p. 5965-5975 11 p., 7169602

Research output: Contribution to journalArticle

Frequency hopping
Frequency shift keying
Sampling
Signal to noise ratio
Bit error rate
2014
15 Citations

Analysis of one-step majority logic decoding under correlated data-dependent gate failures

Brkic, S., Ivanis, P. & Vasic, B. 2014 IEEE International Symposium on Information Theory - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 2599-2603 5 p. 6875304

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Majority logic
Correlated Data
Bit error rate
Markov processes
Decoding
2 Citations

Check-hybrid GLDPC codes: Systematic elimination of trapping sets by super checks

Ravanmehr, V., Declercq, D. & Vasic, B. 2014 IEEE International Symposium on Information Theory - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 701-705 5 p. 6874923

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low-density Parity-check (LDPC) Codes
Trapping
Elimination
LDPC Codes
Eliminate