We introduce novel ten (10T) and eight (8T) transistor full-adder logic gates based on recently proposed gate workfunction engineering (WFE) approach. When applied to sub-10 nm Schottky-barrier (SB) independent-gate FinFETs, WFE leads to hitherto unexplored 4T and 3T XOR implementations that operate with either only one or no inverted input, respectively. The novel 4T and 3T XOR gates eliminate the need for inverted inputs provided that ambipolar I-V characteristics is shifted by the associated gate work-function in the right direction, where another conduction channel exists. Following the logic verification of the novel 4T and 3T XOR gates via TCAD simulations, we then continue to show how these novel gates can be put to use in building ultra-compact 10T and 8T full-adder circuits, which would normally require up to 20 FinFETs in conventional CMOS architecture. Simulated power-delay products of the novel full-adders show significant (∼5×) improvement in dynamic performance attributed largely to the 50% reduction in total area as well as parasitics, at the expense of loss in noise margins. Besides the full-adders explored, the presented WFE approach could in general provide area and performance gains also for other logic building blocks that can be redesigned using SB-FinFETs.