3D printed electronics with high performance, multi-layered electrical interconnect

Chiyen Kim, David Espalin, Min Liang, Hao Xin, Alejandro Cuaron, Issac Varela, Eric Macdonald, Ryan B. Wicker

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

2-D printed electronics have been the focus of intense research for the past two decades primarily focused on implementing electrical interconnect by dispensing conductive binder-based inks. More recently, traditional printed electronics processes have been leveraged within 3-D printed structures where components and interconnect are introduced during fabrication interruptions. The dielectric performance of 3-D printed materials compares well with traditional printed circuit board (PCB) dielectrics but one remaining challenge is the low conductivity of printed ink traces. The performance degradation is due to curing temperature limits imposed by the properties of the polymer substrates. Thermoplastics, such as ULTEM, can maintain form at over 200 C, but production ink curing processes require 850 C to provide an appropriate conductivity. Previous reports have described submerging wires with selective energy within a thermoplastic substrate upon which 3-D printing can continue uninhibited. As copper wires have the same conductivity as PCBs and can be implemented in a wide range of cross-sectional areas, 3-D printed electronics are now in a position to transform the electronics industry. This paper describes an inter-layer process to insert metal connection between layers—allowing for improved routing density and leveraging the geometries brought to bear by 3-D printing. Minimum placement distance between these 3-D printed vias was initially 1.5 mm, and the vias can connect layers separated by as much as 2.8 mm in the vertical build direction (z-axis). As the number of wires layers that can be fabricated is not as limited as traditional board lamination, complex routing can be realized within mass customized, arbitrary shapes.

Original languageEnglish (US)
Article number8107678
Pages (from-to)25286-25294
Number of pages9
JournalIEEE Access
Volume5
DOIs
StatePublished - Jan 1 2017

Fingerprint

Ink
Electronic equipment
Wire
Thermoplastics
Curing
Printing
Electronics industry
Polychlorinated Biphenyls
Substrates
Polychlorinated biphenyls
Printed circuit boards
Binders
Copper
Polymers
Metals
Fabrication
Degradation
Geometry
Temperature

Keywords

  • 3D printed electronics
  • Additive manufacturing
  • Hybrid manufacturing

ASJC Scopus subject areas

  • Computer Science(all)
  • Materials Science(all)
  • Engineering(all)

Cite this

Kim, C., Espalin, D., Liang, M., Xin, H., Cuaron, A., Varela, I., ... Wicker, R. B. (2017). 3D printed electronics with high performance, multi-layered electrical interconnect. IEEE Access, 5, 25286-25294. [8107678]. https://doi.org/10.1109/ACCESS.2017.2773571

3D printed electronics with high performance, multi-layered electrical interconnect. / Kim, Chiyen; Espalin, David; Liang, Min; Xin, Hao; Cuaron, Alejandro; Varela, Issac; Macdonald, Eric; Wicker, Ryan B.

In: IEEE Access, Vol. 5, 8107678, 01.01.2017, p. 25286-25294.

Research output: Contribution to journalArticle

Kim, C, Espalin, D, Liang, M, Xin, H, Cuaron, A, Varela, I, Macdonald, E & Wicker, RB 2017, '3D printed electronics with high performance, multi-layered electrical interconnect', IEEE Access, vol. 5, 8107678, pp. 25286-25294. https://doi.org/10.1109/ACCESS.2017.2773571
Kim, Chiyen ; Espalin, David ; Liang, Min ; Xin, Hao ; Cuaron, Alejandro ; Varela, Issac ; Macdonald, Eric ; Wicker, Ryan B. / 3D printed electronics with high performance, multi-layered electrical interconnect. In: IEEE Access. 2017 ; Vol. 5. pp. 25286-25294.
@article{941c2d8ec8ae44d88e9cbf74210ee2b6,
title = "3D printed electronics with high performance, multi-layered electrical interconnect",
abstract = "2-D printed electronics have been the focus of intense research for the past two decades primarily focused on implementing electrical interconnect by dispensing conductive binder-based inks. More recently, traditional printed electronics processes have been leveraged within 3-D printed structures where components and interconnect are introduced during fabrication interruptions. The dielectric performance of 3-D printed materials compares well with traditional printed circuit board (PCB) dielectrics but one remaining challenge is the low conductivity of printed ink traces. The performance degradation is due to curing temperature limits imposed by the properties of the polymer substrates. Thermoplastics, such as ULTEM, can maintain form at over 200 ◦C, but production ink curing processes require 850 ◦C to provide an appropriate conductivity. Previous reports have described submerging wires with selective energy within a thermoplastic substrate upon which 3-D printing can continue uninhibited. As copper wires have the same conductivity as PCBs and can be implemented in a wide range of cross-sectional areas, 3-D printed electronics are now in a position to transform the electronics industry. This paper describes an inter-layer process to insert metal connection between layers—allowing for improved routing density and leveraging the geometries brought to bear by 3-D printing. Minimum placement distance between these 3-D printed vias was initially 1.5 mm, and the vias can connect layers separated by as much as 2.8 mm in the vertical build direction (z-axis). As the number of wires layers that can be fabricated is not as limited as traditional board lamination, complex routing can be realized within mass customized, arbitrary shapes.",
keywords = "3D printed electronics, Additive manufacturing, Hybrid manufacturing",
author = "Chiyen Kim and David Espalin and Min Liang and Hao Xin and Alejandro Cuaron and Issac Varela and Eric Macdonald and Wicker, {Ryan B.}",
year = "2017",
month = "1",
day = "1",
doi = "10.1109/ACCESS.2017.2773571",
language = "English (US)",
volume = "5",
pages = "25286--25294",
journal = "IEEE Access",
issn = "2169-3536",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - 3D printed electronics with high performance, multi-layered electrical interconnect

AU - Kim, Chiyen

AU - Espalin, David

AU - Liang, Min

AU - Xin, Hao

AU - Cuaron, Alejandro

AU - Varela, Issac

AU - Macdonald, Eric

AU - Wicker, Ryan B.

PY - 2017/1/1

Y1 - 2017/1/1

N2 - 2-D printed electronics have been the focus of intense research for the past two decades primarily focused on implementing electrical interconnect by dispensing conductive binder-based inks. More recently, traditional printed electronics processes have been leveraged within 3-D printed structures where components and interconnect are introduced during fabrication interruptions. The dielectric performance of 3-D printed materials compares well with traditional printed circuit board (PCB) dielectrics but one remaining challenge is the low conductivity of printed ink traces. The performance degradation is due to curing temperature limits imposed by the properties of the polymer substrates. Thermoplastics, such as ULTEM, can maintain form at over 200 ◦C, but production ink curing processes require 850 ◦C to provide an appropriate conductivity. Previous reports have described submerging wires with selective energy within a thermoplastic substrate upon which 3-D printing can continue uninhibited. As copper wires have the same conductivity as PCBs and can be implemented in a wide range of cross-sectional areas, 3-D printed electronics are now in a position to transform the electronics industry. This paper describes an inter-layer process to insert metal connection between layers—allowing for improved routing density and leveraging the geometries brought to bear by 3-D printing. Minimum placement distance between these 3-D printed vias was initially 1.5 mm, and the vias can connect layers separated by as much as 2.8 mm in the vertical build direction (z-axis). As the number of wires layers that can be fabricated is not as limited as traditional board lamination, complex routing can be realized within mass customized, arbitrary shapes.

AB - 2-D printed electronics have been the focus of intense research for the past two decades primarily focused on implementing electrical interconnect by dispensing conductive binder-based inks. More recently, traditional printed electronics processes have been leveraged within 3-D printed structures where components and interconnect are introduced during fabrication interruptions. The dielectric performance of 3-D printed materials compares well with traditional printed circuit board (PCB) dielectrics but one remaining challenge is the low conductivity of printed ink traces. The performance degradation is due to curing temperature limits imposed by the properties of the polymer substrates. Thermoplastics, such as ULTEM, can maintain form at over 200 ◦C, but production ink curing processes require 850 ◦C to provide an appropriate conductivity. Previous reports have described submerging wires with selective energy within a thermoplastic substrate upon which 3-D printing can continue uninhibited. As copper wires have the same conductivity as PCBs and can be implemented in a wide range of cross-sectional areas, 3-D printed electronics are now in a position to transform the electronics industry. This paper describes an inter-layer process to insert metal connection between layers—allowing for improved routing density and leveraging the geometries brought to bear by 3-D printing. Minimum placement distance between these 3-D printed vias was initially 1.5 mm, and the vias can connect layers separated by as much as 2.8 mm in the vertical build direction (z-axis). As the number of wires layers that can be fabricated is not as limited as traditional board lamination, complex routing can be realized within mass customized, arbitrary shapes.

KW - 3D printed electronics

KW - Additive manufacturing

KW - Hybrid manufacturing

UR - http://www.scopus.com/inward/record.url?scp=85047745080&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85047745080&partnerID=8YFLogxK

U2 - 10.1109/ACCESS.2017.2773571

DO - 10.1109/ACCESS.2017.2773571

M3 - Article

AN - SCOPUS:85047745080

VL - 5

SP - 25286

EP - 25294

JO - IEEE Access

JF - IEEE Access

SN - 2169-3536

M1 - 8107678

ER -