A 320MHz-2.56GHz low jitter phase-locked loop with adaptive-bandwidth technique

Seok Min Jung, Janet Meiling Roveda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents a novel adaptive-bandwidth phase-locked loop (PLL) using a closed loop voltage controlled oscillator (VCO). The adaptive-bandwidth PLL uses the gain of closed loop VCO to obtain a constant unity gain bandwidth over an operating frequency range. Furthermore, a charge pump (CP) current is proportional to the current of VCO so that CP current is in proportion to the VCO frequency. Since the adaptive-bandwidth is optimized over the VCO frequency, an integrated RMS jitter is reduced in comparison to a conventional fixed-bandwidth PLL. We simulate the proposed PLL in 130 nm CMOS technology at 1.2 V power supply. The integrated RMS jitter of the proposed adaptive-bandwidth PLL is 2.35 psec which is 70% smaller than the conventional PLL. This adaptive-bandwidth PLL consumes 2.6 mW at 2.56 GHz output frequency.

Original languageEnglish (US)
Title of host publicationProceedings - 28th IEEE International System on Chip Conference, SOCC 2015
EditorsThomas Buchner, Danella Zhao, Karan Bhatia, Ramalingam Sridhar
PublisherIEEE Computer Society
Pages40-43
Number of pages4
ISBN (Electronic)9781467390934
DOIs
StatePublished - Feb 12 2016
Event28th IEEE International System on Chip Conference, SOCC 2015 - Beijing, China
Duration: Sep 8 2015Sep 11 2015

Publication series

NameInternational System on Chip Conference
Volume2016-February
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Other

Other28th IEEE International System on Chip Conference, SOCC 2015
CountryChina
CityBeijing
Period9/8/159/11/15

Keywords

  • adaptive-bandwidth
  • closed loop voltage controlled oscillator (VCO)
  • jitter
  • phase-locked loop (PLL)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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    Jung, S. M., & Roveda, J. M. (2016). A 320MHz-2.56GHz low jitter phase-locked loop with adaptive-bandwidth technique. In T. Buchner, D. Zhao, K. Bhatia, & R. Sridhar (Eds.), Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015 (pp. 40-43). [7406906] (International System on Chip Conference; Vol. 2016-February). IEEE Computer Society. https://doi.org/10.1109/SOCC.2015.7406906