A clustering based area I/O planning for flip-chip technology

Janet Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

The complexity of nanometer SoC design requires the co-design and development of circuit design and packaging technology to enable a successful 'total integrated solution'. In this paper we introduce a new area I/O algorithm for the recent flip-chip packaging technology. The algorithm combines a clustering technique with area I/O planning algorithm to avoid iterations during "placement and area I/O pad assignment". Experiment results show that the total interconnect length (including both on-chip and off-chip parts) and delay are reduced by 10-15% comparing with traditional algorithms.

Original languageEnglish (US)
Title of host publicationProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
PublisherIEEE Computer Society
Pages196-201
Number of pages6
ISBN (Print)0769520936, 9780769520933
DOIs
StatePublished - Jan 1 2004
EventProceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004 - San Jose, CA, United States
Duration: Mar 22 2004Mar 24 2004

Publication series

NameProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Conference

ConferenceProceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004
CountryUnited States
CitySan Jose, CA
Period3/22/043/24/04

ASJC Scopus subject areas

  • Engineering(all)

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