A clustering based area I/O planning for flip-chip technology

Meiling Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The complexity of nanometer SoC design requires the co-design and development of circuit design and packaging technology to enable a successful 'total integrated solution'. In this paper we introduce a new area I/O algorithm for the recent flip-chip packaging technology. The algorithm combines a clustering technique with area I/O planning algorithm to avoid iterations during "placement and area I/O pad assignment". Experiment results show that the total interconnect length (including both on-chip and off-chip parts) and delay are reduced by 10-15% comparing with traditional algorithms.

Original languageEnglish (US)
Title of host publicationProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
Pages196-201
Number of pages6
DOIs
StatePublished - 2004
EventProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004 - San Jose, CA, United States
Duration: Mar 22 2004Mar 24 2004

Other

OtherProceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
CountryUnited States
CitySan Jose, CA
Period3/22/043/24/04

Fingerprint

Planning
Packaging
Networks (circuits)
Experiments
System-on-chip

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Wang, M., Muchherla, K. K., & Kumar, J. G. (2004). A clustering based area I/O planning for flip-chip technology. In Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004 (pp. 196-201) https://doi.org/10.1109/ISQED.2004.1283673

A clustering based area I/O planning for flip-chip technology. / Wang, Meiling; Muchherla, Kishore Kumar; Kumar, Jai Ganesh.

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004. 2004. p. 196-201.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, M, Muchherla, KK & Kumar, JG 2004, A clustering based area I/O planning for flip-chip technology. in Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004. pp. 196-201, Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004, San Jose, CA, United States, 3/22/04. https://doi.org/10.1109/ISQED.2004.1283673
Wang M, Muchherla KK, Kumar JG. A clustering based area I/O planning for flip-chip technology. In Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004. 2004. p. 196-201 https://doi.org/10.1109/ISQED.2004.1283673
Wang, Meiling ; Muchherla, Kishore Kumar ; Kumar, Jai Ganesh. / A clustering based area I/O planning for flip-chip technology. Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004. 2004. pp. 196-201
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