A Codesigned On-Chip Logic Minimizer

Roman L Lysecky, Frank Vahid

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic use in embedded systems, including network route table reduction, network access control list table reduction, and dynamic hardware/software partitioning. These new uses require logic minimization to run dynamically as part of an embedded system's active operation. Performing such dynamic logic minimization on-chip greatly reduces system complexity and security versus an approach that involves communication with a desktop logic minimizer. An on-chip minimizer must be exceptionally lean yet yield good enough results. Previous software-only on-chip minimizer results have been good, but we show that a codesigned minimizer can be much better, executing nearly 8 times faster and consuming nearly 60% less energy, while yielding identical results.

Original languageEnglish (US)
Title of host publicationHardware/Software Codesign - Proceedings of the International Workshop
Pages109-113
Number of pages5
DOIs
StatePublished - 2003
Externally publishedYes
EventFirst IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003 - Newport Beach, CA, United States
Duration: Oct 1 2003Oct 3 2003

Other

OtherFirst IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003
CountryUnited States
CityNewport Beach, CA
Period10/1/0310/3/03

Fingerprint

Embedded systems
Access control
Personal computers
Hardware
Communication
Logic Synthesis

Keywords

  • Dynamic optimization
  • Embedded CAD
  • Embedded systems
  • Hardware/software codesign
  • Logic minimization
  • On-chip logic minimization
  • On-chip synthesis
  • System-on-a-chip

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Lysecky, R. L., & Vahid, F. (2003). A Codesigned On-Chip Logic Minimizer. In Hardware/Software Codesign - Proceedings of the International Workshop (pp. 109-113) https://doi.org/10.1145/944674.944677

A Codesigned On-Chip Logic Minimizer. / Lysecky, Roman L; Vahid, Frank.

Hardware/Software Codesign - Proceedings of the International Workshop. 2003. p. 109-113.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lysecky, RL & Vahid, F 2003, A Codesigned On-Chip Logic Minimizer. in Hardware/Software Codesign - Proceedings of the International Workshop. pp. 109-113, First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, United States, 10/1/03. https://doi.org/10.1145/944674.944677
Lysecky RL, Vahid F. A Codesigned On-Chip Logic Minimizer. In Hardware/Software Codesign - Proceedings of the International Workshop. 2003. p. 109-113 https://doi.org/10.1145/944674.944677
Lysecky, Roman L ; Vahid, Frank. / A Codesigned On-Chip Logic Minimizer. Hardware/Software Codesign - Proceedings of the International Workshop. 2003. pp. 109-113
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