A configurable logic architecture for dynamic hardware/software partitioning

Roman L Lysecky, Frank Vahid

Research output: Chapter in Book/Report/Conference proceedingConference contribution

50 Citations (Scopus)

Abstract

In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently partitioned to execute as a hardware coprocessor on configurable logic - an approach we call warp processing. The configurable logic place and route step is the most computationally intensive part of such hardware/software partitioning, normally running for many minutes or hours on powerful desktop processors. In contrast, dynamic partitioning requires place and route to execute in just seconds and on a lean embedded processor. We have therefore designed a configurable logic architecture specifically for dynamic hardware/software partitioning. Through experiments with popular benchmarks, we show that by specifically focusing on the goal of software kernel speedup when designing the FPGA architecture, rather than on the more general goal of ASIC prototyping, we can perform place and route for our architecture 50 times faster, using 10,000 times less data memory, and 1,000 times less code memory, than popular commercial tools mapping to commercial configurable logic. Yet, we show that we obtain speedups (2x on average, and as much as 4x) and energy savings (33% on average, and up to 74%) when partitioning even just one loop, which are comparable to commercial tools and fabrics. Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software partitioning, and even for fast configurable logic design in general.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition
EditorsG. Gielen, J. Figueras
Pages480-485
Number of pages6
Volume1
DOIs
StatePublished - 2004
Externally publishedYes
EventProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France
Duration: Feb 16 2004Feb 20 2004

Other

OtherProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
CountryFrance
CityParis
Period2/16/042/20/04

Fingerprint

Hardware
Data storage equipment
Logic design
Application specific integrated circuits
Field programmable gate arrays (FPGA)
Energy conservation
Processing
Experiments

Keywords

  • Codesign
  • Configurable logic
  • Dynamic optimization
  • FPGA fabric
  • Hardware/software partitioning
  • Just-in-time compilation
  • Place and route
  • Platforms
  • Reconfigurable computing
  • Self-improving chips
  • Synthesis
  • System-on-a-chip
  • Warp processors

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lysecky, R. L., & Vahid, F. (2004). A configurable logic architecture for dynamic hardware/software partitioning. In G. Gielen, & J. Figueras (Eds.), Proceedings - Design, Automation and Test in Europe Conference and Exhibition (Vol. 1, pp. 480-485) https://doi.org/10.1109/DATE.2004.1268892

A configurable logic architecture for dynamic hardware/software partitioning. / Lysecky, Roman L; Vahid, Frank.

Proceedings - Design, Automation and Test in Europe Conference and Exhibition. ed. / G. Gielen; J. Figueras. Vol. 1 2004. p. 480-485.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lysecky, RL & Vahid, F 2004, A configurable logic architecture for dynamic hardware/software partitioning. in G Gielen & J Figueras (eds), Proceedings - Design, Automation and Test in Europe Conference and Exhibition. vol. 1, pp. 480-485, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, France, 2/16/04. https://doi.org/10.1109/DATE.2004.1268892
Lysecky RL, Vahid F. A configurable logic architecture for dynamic hardware/software partitioning. In Gielen G, Figueras J, editors, Proceedings - Design, Automation and Test in Europe Conference and Exhibition. Vol. 1. 2004. p. 480-485 https://doi.org/10.1109/DATE.2004.1268892
Lysecky, Roman L ; Vahid, Frank. / A configurable logic architecture for dynamic hardware/software partitioning. Proceedings - Design, Automation and Test in Europe Conference and Exhibition. editor / G. Gielen ; J. Figueras. Vol. 1 2004. pp. 480-485
@inproceedings{adf3c7e0853c41879a4d615a1ec4d467,
title = "A configurable logic architecture for dynamic hardware/software partitioning",
abstract = "In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently partitioned to execute as a hardware coprocessor on configurable logic - an approach we call warp processing. The configurable logic place and route step is the most computationally intensive part of such hardware/software partitioning, normally running for many minutes or hours on powerful desktop processors. In contrast, dynamic partitioning requires place and route to execute in just seconds and on a lean embedded processor. We have therefore designed a configurable logic architecture specifically for dynamic hardware/software partitioning. Through experiments with popular benchmarks, we show that by specifically focusing on the goal of software kernel speedup when designing the FPGA architecture, rather than on the more general goal of ASIC prototyping, we can perform place and route for our architecture 50 times faster, using 10,000 times less data memory, and 1,000 times less code memory, than popular commercial tools mapping to commercial configurable logic. Yet, we show that we obtain speedups (2x on average, and as much as 4x) and energy savings (33{\%} on average, and up to 74{\%}) when partitioning even just one loop, which are comparable to commercial tools and fabrics. Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software partitioning, and even for fast configurable logic design in general.",
keywords = "Codesign, Configurable logic, Dynamic optimization, FPGA fabric, Hardware/software partitioning, Just-in-time compilation, Place and route, Platforms, Reconfigurable computing, Self-improving chips, Synthesis, System-on-a-chip, Warp processors",
author = "Lysecky, {Roman L} and Frank Vahid",
year = "2004",
doi = "10.1109/DATE.2004.1268892",
language = "English (US)",
isbn = "0769520855",
volume = "1",
pages = "480--485",
editor = "G. Gielen and J. Figueras",
booktitle = "Proceedings - Design, Automation and Test in Europe Conference and Exhibition",

}

TY - GEN

T1 - A configurable logic architecture for dynamic hardware/software partitioning

AU - Lysecky, Roman L

AU - Vahid, Frank

PY - 2004

Y1 - 2004

N2 - In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently partitioned to execute as a hardware coprocessor on configurable logic - an approach we call warp processing. The configurable logic place and route step is the most computationally intensive part of such hardware/software partitioning, normally running for many minutes or hours on powerful desktop processors. In contrast, dynamic partitioning requires place and route to execute in just seconds and on a lean embedded processor. We have therefore designed a configurable logic architecture specifically for dynamic hardware/software partitioning. Through experiments with popular benchmarks, we show that by specifically focusing on the goal of software kernel speedup when designing the FPGA architecture, rather than on the more general goal of ASIC prototyping, we can perform place and route for our architecture 50 times faster, using 10,000 times less data memory, and 1,000 times less code memory, than popular commercial tools mapping to commercial configurable logic. Yet, we show that we obtain speedups (2x on average, and as much as 4x) and energy savings (33% on average, and up to 74%) when partitioning even just one loop, which are comparable to commercial tools and fabrics. Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software partitioning, and even for fast configurable logic design in general.

AB - In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently partitioned to execute as a hardware coprocessor on configurable logic - an approach we call warp processing. The configurable logic place and route step is the most computationally intensive part of such hardware/software partitioning, normally running for many minutes or hours on powerful desktop processors. In contrast, dynamic partitioning requires place and route to execute in just seconds and on a lean embedded processor. We have therefore designed a configurable logic architecture specifically for dynamic hardware/software partitioning. Through experiments with popular benchmarks, we show that by specifically focusing on the goal of software kernel speedup when designing the FPGA architecture, rather than on the more general goal of ASIC prototyping, we can perform place and route for our architecture 50 times faster, using 10,000 times less data memory, and 1,000 times less code memory, than popular commercial tools mapping to commercial configurable logic. Yet, we show that we obtain speedups (2x on average, and as much as 4x) and energy savings (33% on average, and up to 74%) when partitioning even just one loop, which are comparable to commercial tools and fabrics. Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software partitioning, and even for fast configurable logic design in general.

KW - Codesign

KW - Configurable logic

KW - Dynamic optimization

KW - FPGA fabric

KW - Hardware/software partitioning

KW - Just-in-time compilation

KW - Place and route

KW - Platforms

KW - Reconfigurable computing

KW - Self-improving chips

KW - Synthesis

KW - System-on-a-chip

KW - Warp processors

UR - http://www.scopus.com/inward/record.url?scp=3042658598&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=3042658598&partnerID=8YFLogxK

U2 - 10.1109/DATE.2004.1268892

DO - 10.1109/DATE.2004.1268892

M3 - Conference contribution

AN - SCOPUS:3042658598

SN - 0769520855

SN - 9780769520858

VL - 1

SP - 480

EP - 485

BT - Proceedings - Design, Automation and Test in Europe Conference and Exhibition

A2 - Gielen, G.

A2 - Figueras, J.

ER -