A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

Rexford D. Newbould, Jo Dale Carothers, Jeffrey J Rodriguez, W. Timothy Holman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - 2002
Event2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
Duration: May 26 2002May 29 2002

Other

Other2002 IEEE International Symposium on Circuits and Systems
CountryUnited States
CityPhoenix, AZ
Period5/26/025/29/02

Fingerprint

Intellectual property
Watermarking
Networks (circuits)
Integrated circuit design

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Newbould, R. D., Carothers, J. D., Rodriguez, J. J., & Holman, W. T. (2002). A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 4)

A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs. / Newbould, Rexford D.; Carothers, Jo Dale; Rodriguez, Jeffrey J; Holman, W. Timothy.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4 2002.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Newbould, RD, Carothers, JD, Rodriguez, JJ & Holman, WT 2002, A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 4, 2002 IEEE International Symposium on Circuits and Systems, Phoenix, AZ, United States, 5/26/02.
Newbould RD, Carothers JD, Rodriguez JJ, Holman WT. A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4. 2002
Newbould, Rexford D. ; Carothers, Jo Dale ; Rodriguez, Jeffrey J ; Holman, W. Timothy. / A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 4 2002.
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