A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

Rexford D. Newbould, Jo Dale Carothers, Jeffrey J. Rodriguez, W. Timothy Holman

Research output: Contribution to journalConference article

8 Scopus citations


A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.

Original languageEnglish (US)
Pages (from-to)IV/862-IV/865
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Jan 1 2002
Event2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
Duration: May 26 2002May 29 2002


ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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