A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.
|Original language||English (US)|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 2002|
|Event||2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States|
Duration: May 26 2002 → May 29 2002
ASJC Scopus subject areas
- Electrical and Electronic Engineering