A highly parallel FPGA based IEEE-754 compliant double-precision binary floating-point multiplication algorithm

Sandeep K. Venishetti, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

There is increasing demand for fast floating-point arithmetic support to make Field Programmable Gate Arrays (FPGAs) a practical option for scientific applications. We propose a new IEEE-754 compliant double-precision floating-point multiplication algorithm that supports denormal numbers, NaN and exception handling. Solution involves bit-level operations with minimum dependency between partial products through a specialized adder tree structure tailored to make use of modular and parallel nature of FPGAs. We achieve maximum operational frequency of 274MHz for mantissa multiplication and 228MHz for the overall system on Xilinx Virtex-4 platform. Our design carries performance benefits similar to ASIC based algorithms; and routing benefits similar to ripple carry array and carry save multipliers. Proposed approach outperforms algorithm and IP-Core solutions in the academia and Xilinx LogiCORE multiplier when no embedded resources are used. Algorithm allows reaching double-double precision level with much less performance degradation and pipelining demand than IP-Core based approaches.

Original languageEnglish (US)
Title of host publicationICFPT 2007 - International Conference on Field Programmable Technology
Pages145-152
Number of pages8
DOIs
StatePublished - Dec 1 2007
EventInternational Conference on Field Programmable Technology, ICFPT 2007 - Kitakyushu, Japan
Duration: Dec 12 2007Dec 14 2007

Publication series

NameICFPT 2007 - International Conference on Field Programmable Technology

Other

OtherInternational Conference on Field Programmable Technology, ICFPT 2007
CountryJapan
CityKitakyushu
Period12/12/0712/14/07

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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