A hybrid FPGA model to estimate on-chip crossbar logic utilization in soc platforms

Yoon Kah Leow, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

FPGA analytical models, that express the relationship between architectural parameters (e.g., LUT size, cluster size, inputs per cluster, etc) and performance (e.g., logic utilization, critical path delay, power, etc), have been designed mainly for island-style FPGAs targeting a general application. Therefore, most analytical models will produce inaccurate results when heterogeneous FPGA architectures are targeted. Furthermore, the inherent continuous nature of mathematical models also prevent them from capturing the discrete effects of uniform circuits. Example of such circuits are crossbar switches and barrel shifters. In this paper, we derive a biased model that captures the discrete effects with respect to the logic utilization of crossbar switches by varying the LUT size.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013
PublisherIEEE Computer Society
Pages239-246
Number of pages8
ISBN (Print)9780769549798
DOIs
StatePublished - Jan 1 2013
Event2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013 - Boston, MA, Japan
Duration: Jul 22 2013Jul 26 2013

Publication series

NameProceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013

Conference

Conference2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013
CountryJapan
CityBoston, MA
Period7/22/137/26/13

Keywords

  • crossbar switches
  • discrete effects
  • logic utilization

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Software
  • Theoretical Computer Science

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  • Cite this

    Leow, Y. K., & Akoglu, A. (2013). A hybrid FPGA model to estimate on-chip crossbar logic utilization in soc platforms. In Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013 (pp. 239-246). [6650891] (Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013). IEEE Computer Society. https://doi.org/10.1109/IPDPSW.2013.138