A methodology for cognitive NoC design

Wo Tak Wu, Ahmed Louri

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

The number of cores in a multicore chip design has been increasing in the past two decades. The rate of increase will continue for the foreseeable future. With a large number of cores, the on-chip communication has become a very important design consideration. The increasing number of cores will push the communication complexity level to a point where managing such highly complex systems requires much more than what designers can anticipate for. We propose a new design methodology for implementing a cognitive network-on-chip that has the ability to recognize changes in the environment and to learn new ways to adapt to the changes. This learning capability provides a way for the network to manage itself. Individual network nodes work autonomously to achieve global system goals, e.g., low network latency, higher reliability, power efficiency, adaptability, etc. We use fault-tolerant routing as a case study. Simulation results show that the cognitive design has the potential to outperform the conventional design for large applications. With the great inherent flexibility to adopt different algorithms, the cognitive design can be applied to many applications.

Original languageEnglish (US)
Article number7128666
Pages (from-to)1-4
Number of pages4
JournalIEEE Computer Architecture Letters
Volume15
Issue number1
DOIs
StatePublished - Jan 1 2016

Fingerprint

Communication
Network-on-chip
Large scale systems

Keywords

  • Adaptive
  • Cognitive process
  • Fault-tolerant
  • Intelligent agent
  • Machine learning
  • Multicore
  • Network-on-chip
  • NoC

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

A methodology for cognitive NoC design. / Wu, Wo Tak; Louri, Ahmed.

In: IEEE Computer Architecture Letters, Vol. 15, No. 1, 7128666, 01.01.2016, p. 1-4.

Research output: Contribution to journalArticle

@article{89e3d222eb3e4b44bc145fc76954386e,
title = "A methodology for cognitive NoC design",
abstract = "The number of cores in a multicore chip design has been increasing in the past two decades. The rate of increase will continue for the foreseeable future. With a large number of cores, the on-chip communication has become a very important design consideration. The increasing number of cores will push the communication complexity level to a point where managing such highly complex systems requires much more than what designers can anticipate for. We propose a new design methodology for implementing a cognitive network-on-chip that has the ability to recognize changes in the environment and to learn new ways to adapt to the changes. This learning capability provides a way for the network to manage itself. Individual network nodes work autonomously to achieve global system goals, e.g., low network latency, higher reliability, power efficiency, adaptability, etc. We use fault-tolerant routing as a case study. Simulation results show that the cognitive design has the potential to outperform the conventional design for large applications. With the great inherent flexibility to adopt different algorithms, the cognitive design can be applied to many applications.",
keywords = "Adaptive, Cognitive process, Fault-tolerant, Intelligent agent, Machine learning, Multicore, Network-on-chip, NoC",
author = "Wu, {Wo Tak} and Ahmed Louri",
year = "2016",
month = "1",
day = "1",
doi = "10.1109/LCA.2015.2447535",
language = "English (US)",
volume = "15",
pages = "1--4",
journal = "IEEE Computer Architecture Letters",
issn = "1556-6056",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - A methodology for cognitive NoC design

AU - Wu, Wo Tak

AU - Louri, Ahmed

PY - 2016/1/1

Y1 - 2016/1/1

N2 - The number of cores in a multicore chip design has been increasing in the past two decades. The rate of increase will continue for the foreseeable future. With a large number of cores, the on-chip communication has become a very important design consideration. The increasing number of cores will push the communication complexity level to a point where managing such highly complex systems requires much more than what designers can anticipate for. We propose a new design methodology for implementing a cognitive network-on-chip that has the ability to recognize changes in the environment and to learn new ways to adapt to the changes. This learning capability provides a way for the network to manage itself. Individual network nodes work autonomously to achieve global system goals, e.g., low network latency, higher reliability, power efficiency, adaptability, etc. We use fault-tolerant routing as a case study. Simulation results show that the cognitive design has the potential to outperform the conventional design for large applications. With the great inherent flexibility to adopt different algorithms, the cognitive design can be applied to many applications.

AB - The number of cores in a multicore chip design has been increasing in the past two decades. The rate of increase will continue for the foreseeable future. With a large number of cores, the on-chip communication has become a very important design consideration. The increasing number of cores will push the communication complexity level to a point where managing such highly complex systems requires much more than what designers can anticipate for. We propose a new design methodology for implementing a cognitive network-on-chip that has the ability to recognize changes in the environment and to learn new ways to adapt to the changes. This learning capability provides a way for the network to manage itself. Individual network nodes work autonomously to achieve global system goals, e.g., low network latency, higher reliability, power efficiency, adaptability, etc. We use fault-tolerant routing as a case study. Simulation results show that the cognitive design has the potential to outperform the conventional design for large applications. With the great inherent flexibility to adopt different algorithms, the cognitive design can be applied to many applications.

KW - Adaptive

KW - Cognitive process

KW - Fault-tolerant

KW - Intelligent agent

KW - Machine learning

KW - Multicore

KW - Network-on-chip

KW - NoC

UR - http://www.scopus.com/inward/record.url?scp=84976466226&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84976466226&partnerID=8YFLogxK

U2 - 10.1109/LCA.2015.2447535

DO - 10.1109/LCA.2015.2447535

M3 - Article

VL - 15

SP - 1

EP - 4

JO - IEEE Computer Architecture Letters

JF - IEEE Computer Architecture Letters

SN - 1556-6056

IS - 1

M1 - 7128666

ER -