A multilayer nanophotonic interconnection network for on-chip many-core communications

Xiang Zhang, Ahmed Louri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

37 Citations (Scopus)

Abstract

Multi-core chips or chip multiprocessors (CMPs) are becoming the de facto architecture for scaling up performance and taking advantage of the increasing transistor count on the chip within reasonable power consumption levels. The projected increase in the number of cores in future CMPs is putting stringent demands on the design of the on-chip network (or network-on-chip, NOC). Nanophotonic interconnects have recently emerged as a viable alternate technology solution for the design of NOC because of their higher communication bandwidth, much reduced power consumption and wiring simplification. Several photonic NOC approaches have recently been proposed. A common feature of almost all of these approaches is the integration of the entire optical network onto a single silicon waveguide layer. However, keeping the entire network on a single layer has a serious implication for power losses and design complexity due to the large amount of waveguide crossings. In this paper, we propose MPNOC: a multilayer photonic networks-on-chip. MPNOC combines the recent advances in silicon photonics and three-dimensional (3D) stacking technology with architectural innovations in an integrated architecture that provides ample bandwidth, low latency, and energy efficient on-chip communications for future CMPs. Simulation results show MPNOC can achieve 81.92 TFLOP/s peak bandwidth and an energy savings up to 23% compared to other proposed planar photonic NOC architectures.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages156-161
Number of pages6
DOIs
StatePublished - 2010
Event47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
Duration: Jun 13 2010Jun 18 2010

Other

Other47th Design Automation Conference, DAC '10
CountryUnited States
CityAnaheim, CA
Period6/13/106/18/10

Fingerprint

Nanophotonics
Many-core
Interconnection Networks
Multilayer
Multilayers
Chip
Photonics
Chip multiprocessors
Communication
Bandwidth
Power Consumption
Waveguide
Waveguides
Electric power utilization
Entire
Silicon Photonics
Silicon
Optical Networks
Stacking
Electric wiring

Keywords

  • 3D
  • CMP
  • Interconnection networks
  • Silicon photonics

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

A multilayer nanophotonic interconnection network for on-chip many-core communications. / Zhang, Xiang; Louri, Ahmed.

Proceedings - Design Automation Conference. 2010. p. 156-161.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, X & Louri, A 2010, A multilayer nanophotonic interconnection network for on-chip many-core communications. in Proceedings - Design Automation Conference. pp. 156-161, 47th Design Automation Conference, DAC '10, Anaheim, CA, United States, 6/13/10. https://doi.org/10.1145/1837274.1837314
Zhang, Xiang ; Louri, Ahmed. / A multilayer nanophotonic interconnection network for on-chip many-core communications. Proceedings - Design Automation Conference. 2010. pp. 156-161
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