A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation

Ahmed Louri, Hongki Sung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Summary form only given, as follows. The authors propose a novel compiler-directed cache management scheme which allows parallel invalidation of a subset of array elements. The scheme limits nonstale data invalidations using a novel memory allocation technique. Its correctness is proved using a flow graph model. It is also shown that the scheme provides more cacheability than the previous compiler-directed ones and has lower overhead in determining read hit at runtime. A new performance parameter called unwanted invalidation ratio, for compiler-directed coherence schemes, is also proposed.

Original languageEnglish (US)
Title of host publicationConference Proceedings - Annual Symposium on Computer Architecture
PublisherPubl by IEEE
Number of pages1
ISBN (Print)0897915097
StatePublished - May 1 1992
Event19th International Symposium on Computer Architecture - Gold Coast, Aust
Duration: May 19 1992May 21 1992

Publication series

NameConference Proceedings - Annual Symposium on Computer Architecture

Other

Other19th International Symposium on Computer Architecture
CityGold Coast, Aust
Period5/19/925/21/92

ASJC Scopus subject areas

  • Engineering(all)

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    Louri, A., & Sung, H. (1992). A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. In Conference Proceedings - Annual Symposium on Computer Architecture (Conference Proceedings - Annual Symposium on Computer Architecture). Publ by IEEE.