A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAM

Peter Gadfort, Aravind Dasu, Ali Akoglu, Yoon Kah Leow, Michael Fritze

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Increasing computing power efficiency has become more important as more applications are moving to mobile platforms, which tend to have a limited power available. Being able to perform a wide variety of computations efficiently is especially important for power constrained embedded applications such as unmanned aerial vehicles (UAVs), which may not be able to send the data out for processing and must perform some of the processing on-board. This paper describes a 3D FPGA-DRAM architecture that can not only deliver the necessary flexibility, by using FPGAs, but also provide the computing efficiency in the form of floating-point arithmetic accelerators that is required for UAVs. We examine the efficiency of this system in 65 nm, 90 nm, and 130 nm CMOS technologies and report simulation results showing a peak computing efficiency of 28.94 GFLOPs/W for a 4,096 point 1 dimensional FFT and 25.03 GFLOPs/W for a 1,024 point × 1,024 point 2 dimensional FFT.

Original languageEnglish (US)
Title of host publicationInternational System on Chip Conference
EditorsRamalingam Sridhar, Danella Zhao, Kaijian Shi, Thomas Buchner
PublisherIEEE Computer Society
Pages11-16
Number of pages6
ISBN (Electronic)9781479933785
DOIs
StatePublished - Nov 5 2014
Event27th IEEE International System on Chip Conference, SOCC 2014 - Las Vegas, United States
Duration: Sep 2 2014Sep 5 2014

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Other

Other27th IEEE International System on Chip Conference, SOCC 2014
CountryUnited States
CityLas Vegas
Period9/2/149/5/14

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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    Gadfort, P., Dasu, A., Akoglu, A., Leow, Y. K., & Fritze, M. (2014). A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAM. In R. Sridhar, D. Zhao, K. Shi, & T. Buchner (Eds.), International System on Chip Conference (pp. 11-16). [6948892] (International System on Chip Conference). IEEE Computer Society. https://doi.org/10.1109/SOCC.2014.6948892