A probabilistic analysis of pipelined global interconnect under process variations

Navneeth Kankani, Vineet Agarwal, Meiling Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a novel delay metric named DMA for estimation of interconnect delay probability density function considering process variations. Without considerable loss in accuracy, DMA can achieve high computational efficiency even in a large space of random variables. We then propose a comprehensive probabilistic methodology for sampling transfers, on a shared latch inserted global interconnect, that highly improves the reliability of the interconnect. Improvements up to 125% are observed in the reliability when compared to deterministic sampling approach. It is also shown that dual phase clocking scheme for pipelined global interconnect is able to meet more stringent timing constraints due to its lower latency.

Original languageEnglish (US)
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages724-729
Number of pages6
Volume2006
StatePublished - 2006
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
Duration: Jan 24 2006Jan 27 2006

Other

OtherASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CountryJapan
CityYokohama
Period1/24/061/27/06

Fingerprint

Dynamic mechanical analysis
Sampling
Computational efficiency
Random variables
Probability density function
Uncertainty

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kankani, N., Agarwal, V., & Wang, M. (2006). A probabilistic analysis of pipelined global interconnect under process variations. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 2006, pp. 724-729). [1594772]

A probabilistic analysis of pipelined global interconnect under process variations. / Kankani, Navneeth; Agarwal, Vineet; Wang, Meiling.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006 2006. p. 724-729 1594772.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kankani, N, Agarwal, V & Wang, M 2006, A probabilistic analysis of pipelined global interconnect under process variations. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. vol. 2006, 1594772, pp. 724-729, ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006, Yokohama, Japan, 1/24/06.
Kankani N, Agarwal V, Wang M. A probabilistic analysis of pipelined global interconnect under process variations. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. 2006. p. 724-729. 1594772
Kankani, Navneeth ; Agarwal, Vineet ; Wang, Meiling. / A probabilistic analysis of pipelined global interconnect under process variations. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006 2006. pp. 724-729
@inproceedings{452fbd76cf754638a0f8554074ccf279,
title = "A probabilistic analysis of pipelined global interconnect under process variations",
abstract = "The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a novel delay metric named DMA for estimation of interconnect delay probability density function considering process variations. Without considerable loss in accuracy, DMA can achieve high computational efficiency even in a large space of random variables. We then propose a comprehensive probabilistic methodology for sampling transfers, on a shared latch inserted global interconnect, that highly improves the reliability of the interconnect. Improvements up to 125{\%} are observed in the reliability when compared to deterministic sampling approach. It is also shown that dual phase clocking scheme for pipelined global interconnect is able to meet more stringent timing constraints due to its lower latency.",
author = "Navneeth Kankani and Vineet Agarwal and Meiling Wang",
year = "2006",
language = "English (US)",
isbn = "0780394518",
volume = "2006",
pages = "724--729",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

}

TY - GEN

T1 - A probabilistic analysis of pipelined global interconnect under process variations

AU - Kankani, Navneeth

AU - Agarwal, Vineet

AU - Wang, Meiling

PY - 2006

Y1 - 2006

N2 - The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a novel delay metric named DMA for estimation of interconnect delay probability density function considering process variations. Without considerable loss in accuracy, DMA can achieve high computational efficiency even in a large space of random variables. We then propose a comprehensive probabilistic methodology for sampling transfers, on a shared latch inserted global interconnect, that highly improves the reliability of the interconnect. Improvements up to 125% are observed in the reliability when compared to deterministic sampling approach. It is also shown that dual phase clocking scheme for pipelined global interconnect is able to meet more stringent timing constraints due to its lower latency.

AB - The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a novel delay metric named DMA for estimation of interconnect delay probability density function considering process variations. Without considerable loss in accuracy, DMA can achieve high computational efficiency even in a large space of random variables. We then propose a comprehensive probabilistic methodology for sampling transfers, on a shared latch inserted global interconnect, that highly improves the reliability of the interconnect. Improvements up to 125% are observed in the reliability when compared to deterministic sampling approach. It is also shown that dual phase clocking scheme for pipelined global interconnect is able to meet more stringent timing constraints due to its lower latency.

UR - http://www.scopus.com/inward/record.url?scp=33748609352&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33748609352&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33748609352

SN - 0780394518

SN - 9780780394513

VL - 2006

SP - 724

EP - 729

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

ER -