A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching

Y. Satish Kumar, Jun Li, Claudio Talarico, Janet Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

32 Scopus citations

Abstract

Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching. The proposed model uses orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit timing performance. From the experimental results, our approach has less that 0.2% error on the mean delay of gates and less than 3% error on the standard deviation.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE '05
Pages770-775
Number of pages6
DOIs
StatePublished - Dec 1 2005
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE '05
VolumeII
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Satish Kumar, Y., Li, J., Talarico, C., & Wang, J. (2005). A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching. In Proceedings - Design, Automation and Test in Europe, DATE '05 (pp. 770-775). [1395671] (Proceedings -Design, Automation and Test in Europe, DATE '05; Vol. II). https://doi.org/10.1109/DATE.2005.31