Abstract
Current CMOS technology is reaching its scaling limits and thus the CMOS based devices are slowly being replaced by new nanotechnology devices. These nanotechnology devices, however, pose some simulation challenges due to their non-monotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance of the simulator. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices, avoiding such problems. The experimental results show a 20-30 times speedup comparing with existing simulators.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Pages | 2518-2521 |
| Number of pages | 4 |
| DOIs | |
| State | Published - 2005 |
| Event | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: May 23 2005 → May 26 2005 |
Other
| Other | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 |
|---|---|
| Country | Japan |
| City | Kobe |
| Period | 5/23/05 → 5/26/05 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A stepwise constant conductance approach for simulating resonant tunneling diodes. / Sukhwani, Bharat; Wang, Meiling.
Proceedings - IEEE International Symposium on Circuits and Systems. 2005. p. 2518-2521 1465138.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A stepwise constant conductance approach for simulating resonant tunneling diodes
AU - Sukhwani, Bharat
AU - Wang, Meiling
PY - 2005
Y1 - 2005
N2 - Current CMOS technology is reaching its scaling limits and thus the CMOS based devices are slowly being replaced by new nanotechnology devices. These nanotechnology devices, however, pose some simulation challenges due to their non-monotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance of the simulator. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices, avoiding such problems. The experimental results show a 20-30 times speedup comparing with existing simulators.
AB - Current CMOS technology is reaching its scaling limits and thus the CMOS based devices are slowly being replaced by new nanotechnology devices. These nanotechnology devices, however, pose some simulation challenges due to their non-monotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance of the simulator. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices, avoiding such problems. The experimental results show a 20-30 times speedup comparing with existing simulators.
UR - http://www.scopus.com/inward/record.url?scp=67649120077&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67649120077&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1465138
DO - 10.1109/ISCAS.2005.1465138
M3 - Conference contribution
AN - SCOPUS:67649120077
SP - 2518
EP - 2521
BT - Proceedings - IEEE International Symposium on Circuits and Systems
ER -