A study of the scalability of on-chip routing for just-in-time FPGA compilation

Roman L Lysecky, Frank Vahid, Sheldon X D Tan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously introduced the concept of a standard hardware binary, using a just-in-time compiler to compile the hardware binary to a field-programmable gate array (FPGA). Our JIT compiler includes lean versions of technology mapping, placement, and routing algorithms, of which routing is the most computationally and memory expensive step. As FPGAs continue to increase in size, a JIT FPGA compiler must be capable of efficiently mapping increasingly larger hardware circuits. In this paper, we analyze the scalability of our lean on-chip router, the Riverside On-Chip Router (ROCR), for routing increasingly large hardware circuits. We demonstrate that ROCR scales well in terms of execution time, memory usage and circuit quality, and we compare the scalability of ROCR to the well known Versatile Place and Route (VPR) timing-driven routing algorithm, comparing to both their standard routing algorithm and their fast routing algorithm. Our results show that on average ROCR executes 3 times faster using 18 times less memory than VPR. ROCR requires only 1% more routing resources, while creating a critical path 30% longer VPR's standard timing-driven router. Furthermore, for the largest hardware circuit, ROCR executes 3 times faster using 14 times less memory, and results in a critical path 2.6% shorter than VPR's fast timing-driven router.

Original languageEnglish (US)
Title of host publicationProceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005
Pages57-62
Number of pages6
Volume2005
DOIs
StatePublished - 2005
Externally publishedYes
Event13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005 - Napa, CA, United States
Duration: Apr 18 2005Apr 20 2005

Other

Other13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005
CountryUnited States
CityNapa, CA
Period4/18/054/20/05

Fingerprint

Routers
Field programmable gate arrays (FPGA)
Scalability
Routing algorithms
Hardware
Data storage equipment
Networks (circuits)

Keywords

  • Codesign
  • Configurable logic
  • Dynamic optimization
  • FPGA
  • Hardware/software partitioning
  • Just-in-time (JIT) compilation
  • Place and route
  • Platforms
  • Standard hardware binary
  • System-on-a-chip
  • Warp processors

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lysecky, R. L., Vahid, F., & Tan, S. X. D. (2005). A study of the scalability of on-chip routing for just-in-time FPGA compilation. In Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005 (Vol. 2005, pp. 57-62). [1508526] https://doi.org/10.1109/FCCM.2005.12

A study of the scalability of on-chip routing for just-in-time FPGA compilation. / Lysecky, Roman L; Vahid, Frank; Tan, Sheldon X D.

Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005. Vol. 2005 2005. p. 57-62 1508526.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lysecky, RL, Vahid, F & Tan, SXD 2005, A study of the scalability of on-chip routing for just-in-time FPGA compilation. in Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005. vol. 2005, 1508526, pp. 57-62, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005, Napa, CA, United States, 4/18/05. https://doi.org/10.1109/FCCM.2005.12
Lysecky RL, Vahid F, Tan SXD. A study of the scalability of on-chip routing for just-in-time FPGA compilation. In Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005. Vol. 2005. 2005. p. 57-62. 1508526 https://doi.org/10.1109/FCCM.2005.12
Lysecky, Roman L ; Vahid, Frank ; Tan, Sheldon X D. / A study of the scalability of on-chip routing for just-in-time FPGA compilation. Proceedings - 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005. Vol. 2005 2005. pp. 57-62
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abstract = "Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously introduced the concept of a standard hardware binary, using a just-in-time compiler to compile the hardware binary to a field-programmable gate array (FPGA). Our JIT compiler includes lean versions of technology mapping, placement, and routing algorithms, of which routing is the most computationally and memory expensive step. As FPGAs continue to increase in size, a JIT FPGA compiler must be capable of efficiently mapping increasingly larger hardware circuits. In this paper, we analyze the scalability of our lean on-chip router, the Riverside On-Chip Router (ROCR), for routing increasingly large hardware circuits. We demonstrate that ROCR scales well in terms of execution time, memory usage and circuit quality, and we compare the scalability of ROCR to the well known Versatile Place and Route (VPR) timing-driven routing algorithm, comparing to both their standard routing algorithm and their fast routing algorithm. Our results show that on average ROCR executes 3 times faster using 18 times less memory than VPR. ROCR requires only 1{\%} more routing resources, while creating a critical path 30{\%} longer VPR's standard timing-driven router. Furthermore, for the largest hardware circuit, ROCR executes 3 times faster using 14 times less memory, and results in a critical path 2.6{\%} shorter than VPR's fast timing-driven router.",
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