A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning

Roman L Lysecky, Frank Vahid

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Citations (Scopus)

Abstract

Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to more readily incorporate FPGAs in their designs. FPGA vendors have begun providing configurable soft processor cores that can be synthesized onto their FPGA products. While FPGAs with soft processor cores provide designers with increased flexibility, such processors typically have degraded performance and energy consumption compared to hard-core processors. Previously, we proposed warp processing, a technique capable of optimizing a software application by dynamically and transparently re-implementing critical software kernels as custom circuits in on-chip configurable logic. In this paper, we study the potential of a MicroBlaze soft-core based warp processing system to eliminate the performance and energy overhead of a soft-core processor compared to a hard-core processor. We demonstrate that the soft-core based warp processor achieves average speedups of 5.8 and energy reductions of 57% compared to the soft core alone. Our data shows that a soft-core based warp processor yields performance and energy consumption competitive with existing hard-core processors, thus expanding the usefulness of soft processor cores on FPGAs to a broader range of applications.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE '05
Pages18-23
Number of pages6
VolumeI
DOIs
StatePublished - 2005
Externally publishedYes
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

Fingerprint

Field programmable gate arrays (FPGA)
Hardware
Energy utilization
Networks (circuits)
Processing
Application programs
Costs

Keywords

  • Dynamic optimization
  • FPGA
  • Hardware/software partitioning
  • Microblaze
  • Soft cores
  • Warp processing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lysecky, R. L., & Vahid, F. (2005). A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning. In Proceedings -Design, Automation and Test in Europe, DATE '05 (Vol. I, pp. 18-23). [1395522] https://doi.org/10.1109/DATE.2005.38

A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning. / Lysecky, Roman L; Vahid, Frank.

Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. I 2005. p. 18-23 1395522.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lysecky, RL & Vahid, F 2005, A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning. in Proceedings -Design, Automation and Test in Europe, DATE '05. vol. I, 1395522, pp. 18-23, Design, Automation and Test in Europe, DATE '05, Munich, Germany, 3/7/05. https://doi.org/10.1109/DATE.2005.38
Lysecky RL, Vahid F. A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning. In Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. I. 2005. p. 18-23. 1395522 https://doi.org/10.1109/DATE.2005.38
Lysecky, Roman L ; Vahid, Frank. / A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning. Proceedings -Design, Automation and Test in Europe, DATE '05. Vol. I 2005. pp. 18-23
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