A systematic construction of capacity-achieving irregular low-density parity-check codes

S. Sankaranarayan, Bane V Vasic, E. Kurtas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this paper, we propose symmetric method to split column and rows of parity-check matrix (Hreg) of regular LDPC code in order to construct capacity-achieving irregular LDPC code with a given distribution (Λreq, Ωreq).

Original languageEnglish (US)
Title of host publicationIntermag 2003 - Program of the 2003 IEEE International Magnetics Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)0780376471, 9780780376472
DOIs
Publication statusPublished - 2003
Event2003 IEEE International Magnetics Conference, Intermag 2003 - Boston, United States
Duration: Mar 30 2003Apr 3 2003

Other

Other2003 IEEE International Magnetics Conference, Intermag 2003
CountryUnited States
CityBoston
Period3/30/034/3/03

Keywords

  • Cyclic redundancy check
  • Equations
  • Magnetic recording
  • Optimization methods
  • Parity check codes
  • Partitioning algorithms

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Sankaranarayan, S., Vasic, B. V., & Kurtas, E. (2003). A systematic construction of capacity-achieving irregular low-density parity-check codes. In Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference [1230516] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/INTMAG.2003.1230516