Adaptive inter-router links for low-power, area-efficient and reliable network-on-chip(NoC) architectures

Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, Meiling Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

The increasing wire delay constraints in deep sub- micron VLSI designs have led to the emergence of scalable and modular Network-on-Chip(NoC) architectures. As the power consumption, area overhead and performance of the entire NoC is influenced by the router buffers, research efforts have targeted optimized router buffer design. In this paper, we propose iDEAL - inter-router, dual-function energy and area-efficient links capable of data transmission as well as data storage when required. iDEAL enables a reduction in the router buffer size by controlling the repeaters along the links to adaptively function as link buffers during congestion, thereby achieving nearly 30% savings in overall network power and 35% reduction in area with only a marginal 1- 3% drop in performance. In addition, aggressive speculative flow control further improves the performance of iDEAL. Moreover, the significant reduction in power consumption and area provides sufficient headroom for monitoring Negative Bias Temperature Instability(NBTI) effects in order to improve circuit reliability at reduced feature sizes.

Original languageEnglish (US)
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages1-6
Number of pages6
DOIs
StatePublished - 2009
EventAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan
Duration: Jan 19 2009Jan 22 2009

Other

OtherAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
CountryJapan
CityYokohama
Period1/19/091/22/09

Fingerprint

Routers
Telecommunication links
Electric power utilization
Telecommunication repeaters
Flow control
Data communication systems
Wire
Data storage equipment
Network-on-chip
Networks (circuits)
Monitoring

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Kodi, A. K., Sarathy, A., Louri, A., & Wang, M. (2009). Adaptive inter-router links for low-power, area-efficient and reliable network-on-chip(NoC) architectures. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 1-6). [4796432] https://doi.org/10.1109/ASPDAC.2009.4796432

Adaptive inter-router links for low-power, area-efficient and reliable network-on-chip(NoC) architectures. / Kodi, Avinash Karanth; Sarathy, Ashwini; Louri, Ahmed; Wang, Meiling.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. p. 1-6 4796432.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kodi, AK, Sarathy, A, Louri, A & Wang, M 2009, Adaptive inter-router links for low-power, area-efficient and reliable network-on-chip(NoC) architectures. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4796432, pp. 1-6, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, Japan, 1/19/09. https://doi.org/10.1109/ASPDAC.2009.4796432
Kodi AK, Sarathy A, Louri A, Wang M. Adaptive inter-router links for low-power, area-efficient and reliable network-on-chip(NoC) architectures. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. p. 1-6. 4796432 https://doi.org/10.1109/ASPDAC.2009.4796432
Kodi, Avinash Karanth ; Sarathy, Ashwini ; Louri, Ahmed ; Wang, Meiling. / Adaptive inter-router links for low-power, area-efficient and reliable network-on-chip(NoC) architectures. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. pp. 1-6
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