Ambipolar SB-FinFETs: A New Path to Ultra-Compact Sub-10 nm Logic Circuits

Talha F. Canan, Savas Kaya, Avinash Karanth, Hao Xin, Ahmed Louri

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Ultracompact sub-10-nm logic gates based on ambipolar characteristics of Schottky-barrier (SB) FinFETs and gate workfunction engineering (WFE) approach are introduced. Novel logic gate designs are proposed using WFE, whereby adjustment of workfunction in the contacts as well as two independently biased FinFET gates leads to an unprecedented degree of freedom for logic functionality that has not been explored before. The use of SB contacts, along with the high-k gate dielectric and ultrathin body, bestows a high-degree of short-channel immunity to the SB-FinFETs with ambipolar current-voltage characteristics down to 5 nm. The unique trait of the proposed novel logic gates is to lower CMOS transistor count by 50% and hence reduce overall area and power dissipation significantly. To illustrate this potential, an entirely novel conjugate (n/p channel) CMOS pass-gate transistor that can function as a two-transistor (2T) xor and minimalist 2T nand/nor gates is designed and verified with TCAD simulations. Depending on the gate designed, TCAD simulations indicate that judicious choice of gate workfunctions between 3.7 and 5.2 eV can lead to CMOS logic gates with a power-delay product (PDP) at 5x10⁻¹⁸ J level with immunity to ± 0.1-eV workfunction variations. It is shown that WFE in independent-gate SB-FinFETs can lead to ultracompact logic circuits with 50% reduction in area and up to 10 times reduction in power, without significant degradation to overall PDP performance due to slower switching response compared with the conventional designs with p-n junction FinFET counterparts.

Original languageEnglish (US)
JournalIEEE Transactions on Electron Devices
DOIs
StateAccepted/In press - Jan 1 2018

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Logic circuits
Logic gates
Transistors
Gate dielectrics
Current voltage characteristics
Energy dissipation
FinFET
Degradation
thiazole-4-carboxamide adenine dinucleotide

Keywords

  • Ambipolar
  • Charge carrier processes
  • CMOS logic gates
  • FinFETs
  • Logic gates
  • nanotechnology
  • Schottky-barrier (SB) MOSFET
  • Silicon
  • Tunneling
  • tunneling.

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Ambipolar SB-FinFETs : A New Path to Ultra-Compact Sub-10 nm Logic Circuits. / Canan, Talha F.; Kaya, Savas; Karanth, Avinash; Xin, Hao; Louri, Ahmed.

In: IEEE Transactions on Electron Devices, 01.01.2018.

Research output: Contribution to journalArticle

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abstract = "Ultracompact sub-10-nm logic gates based on ambipolar characteristics of Schottky-barrier (SB) FinFETs and gate workfunction engineering (WFE) approach are introduced. Novel logic gate designs are proposed using WFE, whereby adjustment of workfunction in the contacts as well as two independently biased FinFET gates leads to an unprecedented degree of freedom for logic functionality that has not been explored before. The use of SB contacts, along with the high-k gate dielectric and ultrathin body, bestows a high-degree of short-channel immunity to the SB-FinFETs with ambipolar current-voltage characteristics down to 5 nm. The unique trait of the proposed novel logic gates is to lower CMOS transistor count by 50{\%} and hence reduce overall area and power dissipation significantly. To illustrate this potential, an entirely novel conjugate (n/p channel) CMOS pass-gate transistor that can function as a two-transistor (2T) xor and minimalist 2T nand/nor gates is designed and verified with TCAD simulations. Depending on the gate designed, TCAD simulations indicate that judicious choice of gate workfunctions between 3.7 and 5.2 eV can lead to CMOS logic gates with a power-delay product (PDP) at 5x10⁻¹⁸ J level with immunity to ± 0.1-eV workfunction variations. It is shown that WFE in independent-gate SB-FinFETs can lead to ultracompact logic circuits with 50{\%} reduction in area and up to 10 times reduction in power, without significant degradation to overall PDP performance due to slower switching response compared with the conventional designs with p-n junction FinFET counterparts.",
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