An adaptable low density parity check (LDPC) engine for space based communication systems

Gregory M. Striemer, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Space communication systems are characterized by the severe limitations to the on-board computational power and the tight constraints of received signal strengths. Also, these systems observe degradation in signals caused by large propagation latencies, extreme distances traveled, as well as data corruption causing high biterror rates. LDPC codes provide powerful error correction capability where signal power is very low, making them an ideal candidate for space based applications. A hardware architecture that is configurable to dynamic changes in channel conditions is a necessity for error resilient communication systems. In this study we demonstrate the feasibility of designing an FPGA based adaptable LDPC decoder architecture that also matches the throughput demand of current space based communications requirements. We design an LDPC engine that is adaptable to three code rates by taking advantage of the partial reconfiguration technology and parallel nature of the FPGA architecture. We evaluate the tradeoff between the level of parallelism to exploit on the FPGA when implementing LDPC codes and resource demand for each code rate under the constraints of delivering a partially reconfigurable and adaptable solution. Based on the implementation using a Xilinx Virtex-5 FPGA, our design handles context switching between the codes on board in 92μs.

Original languageEnglish (US)
Title of host publication2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010
Pages105-112
Number of pages8
DOIs
StatePublished - 2010
Event2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010 - Anaheim, CA, United States
Duration: Jun 15 2010Jun 18 2010

Other

Other2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010
CountryUnited States
CityAnaheim, CA
Period6/15/106/18/10

Fingerprint

Field programmable gate arrays (FPGA)
Communication systems
Engines
Error correction
Throughput
Hardware
Degradation
Communication

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Striemer, G. M., & Akoglu, A. (2010). An adaptable low density parity check (LDPC) engine for space based communication systems. In 2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010 (pp. 105-112). [5546275] https://doi.org/10.1109/AHS.2010.5546275

An adaptable low density parity check (LDPC) engine for space based communication systems. / Striemer, Gregory M.; Akoglu, Ali.

2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010. 2010. p. 105-112 5546275.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Striemer, GM & Akoglu, A 2010, An adaptable low density parity check (LDPC) engine for space based communication systems. in 2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010., 5546275, pp. 105-112, 2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010, Anaheim, CA, United States, 6/15/10. https://doi.org/10.1109/AHS.2010.5546275
Striemer GM, Akoglu A. An adaptable low density parity check (LDPC) engine for space based communication systems. In 2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010. 2010. p. 105-112. 5546275 https://doi.org/10.1109/AHS.2010.5546275
Striemer, Gregory M. ; Akoglu, Ali. / An adaptable low density parity check (LDPC) engine for space based communication systems. 2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010. 2010. pp. 105-112
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