An analytical energy model to accelerate FPGA logic architecture investigation

Senthilkumar T. Rajavel, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

There is a pressing need for exploring innovative reconfigurable architectures with the steady growth in the range of FPGA based applications. However, traditional FPGA architecture design methods require time consuming CAD experimentations to identify the most suitable hardware configuration for the target application. Several analytical models have been recently proposed to predict the relative performance of a given set of architectures. Replacing CAD experiments with these analytical models poses as the solution for reducing the complexity of architecture evaluation process. However, among a large set of existing models, an analytical energy model is missing to supplement the architecture evaluation. We argue that energy can be defined as a function of routed wire length and critical path delay. Therefore, we inherit wire length and critical path delay models to derive an analytical energy model for homogeneous FPGA architectures. We evaluate the impact of variations in logic architecture parameters in terms of LUT size, cluster size and inputs per CLB on the energy performance, and show that our energy model accurately captures the trends observed through CAD experiments. An energy model is robust only if its predictions are in agreement with any CAD flow or benchmark suite. We study the robustness of our energy model by varying the seed selection process of placement, optimization goal of clustering and placement, and the nature of the benchmark suite. In all our experimental evaluations, we observe that the energy model accurately captures the performance trends with a high degree of fidelity.

Original languageEnglish (US)
Title of host publication2011 International Conference on Field-Programmable Technology, FPT 2011
DOIs
StatePublished - 2011
Event2011 International Conference on Field-Programmable Technology, FPT 2011 - New Delhi, India
Duration: Dec 12 2011Dec 14 2011

Other

Other2011 International Conference on Field-Programmable Technology, FPT 2011
CountryIndia
CityNew Delhi
Period12/12/1112/14/11

Fingerprint

Energy Model
Analytical Model
Field Programmable Gate Array
Accelerate
Field programmable gate arrays (FPGA)
Logic
Computer aided design
Critical Path
Analytical models
Placement
Benchmark
Reconfigurable Architectures
Wire
Reconfigurable architectures
Evaluation
Energy
Experimental Evaluation
Large Set
Experimentation
Fidelity

ASJC Scopus subject areas

  • Computational Mathematics

Cite this

Rajavel, S. T., & Akoglu, A. (2011). An analytical energy model to accelerate FPGA logic architecture investigation. In 2011 International Conference on Field-Programmable Technology, FPT 2011 [6132683] https://doi.org/10.1109/FPT.2011.6132683

An analytical energy model to accelerate FPGA logic architecture investigation. / Rajavel, Senthilkumar T.; Akoglu, Ali.

2011 International Conference on Field-Programmable Technology, FPT 2011. 2011. 6132683.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rajavel, ST & Akoglu, A 2011, An analytical energy model to accelerate FPGA logic architecture investigation. in 2011 International Conference on Field-Programmable Technology, FPT 2011., 6132683, 2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, 12/12/11. https://doi.org/10.1109/FPT.2011.6132683
Rajavel ST, Akoglu A. An analytical energy model to accelerate FPGA logic architecture investigation. In 2011 International Conference on Field-Programmable Technology, FPT 2011. 2011. 6132683 https://doi.org/10.1109/FPT.2011.6132683
Rajavel, Senthilkumar T. ; Akoglu, Ali. / An analytical energy model to accelerate FPGA logic architecture investigation. 2011 International Conference on Field-Programmable Technology, FPT 2011. 2011.
@inproceedings{9081d0552e1e4c21b8ad681bdea4652a,
title = "An analytical energy model to accelerate FPGA logic architecture investigation",
abstract = "There is a pressing need for exploring innovative reconfigurable architectures with the steady growth in the range of FPGA based applications. However, traditional FPGA architecture design methods require time consuming CAD experimentations to identify the most suitable hardware configuration for the target application. Several analytical models have been recently proposed to predict the relative performance of a given set of architectures. Replacing CAD experiments with these analytical models poses as the solution for reducing the complexity of architecture evaluation process. However, among a large set of existing models, an analytical energy model is missing to supplement the architecture evaluation. We argue that energy can be defined as a function of routed wire length and critical path delay. Therefore, we inherit wire length and critical path delay models to derive an analytical energy model for homogeneous FPGA architectures. We evaluate the impact of variations in logic architecture parameters in terms of LUT size, cluster size and inputs per CLB on the energy performance, and show that our energy model accurately captures the trends observed through CAD experiments. An energy model is robust only if its predictions are in agreement with any CAD flow or benchmark suite. We study the robustness of our energy model by varying the seed selection process of placement, optimization goal of clustering and placement, and the nature of the benchmark suite. In all our experimental evaluations, we observe that the energy model accurately captures the performance trends with a high degree of fidelity.",
author = "Rajavel, {Senthilkumar T.} and Ali Akoglu",
year = "2011",
doi = "10.1109/FPT.2011.6132683",
language = "English (US)",
isbn = "9781457717406",
booktitle = "2011 International Conference on Field-Programmable Technology, FPT 2011",

}

TY - GEN

T1 - An analytical energy model to accelerate FPGA logic architecture investigation

AU - Rajavel, Senthilkumar T.

AU - Akoglu, Ali

PY - 2011

Y1 - 2011

N2 - There is a pressing need for exploring innovative reconfigurable architectures with the steady growth in the range of FPGA based applications. However, traditional FPGA architecture design methods require time consuming CAD experimentations to identify the most suitable hardware configuration for the target application. Several analytical models have been recently proposed to predict the relative performance of a given set of architectures. Replacing CAD experiments with these analytical models poses as the solution for reducing the complexity of architecture evaluation process. However, among a large set of existing models, an analytical energy model is missing to supplement the architecture evaluation. We argue that energy can be defined as a function of routed wire length and critical path delay. Therefore, we inherit wire length and critical path delay models to derive an analytical energy model for homogeneous FPGA architectures. We evaluate the impact of variations in logic architecture parameters in terms of LUT size, cluster size and inputs per CLB on the energy performance, and show that our energy model accurately captures the trends observed through CAD experiments. An energy model is robust only if its predictions are in agreement with any CAD flow or benchmark suite. We study the robustness of our energy model by varying the seed selection process of placement, optimization goal of clustering and placement, and the nature of the benchmark suite. In all our experimental evaluations, we observe that the energy model accurately captures the performance trends with a high degree of fidelity.

AB - There is a pressing need for exploring innovative reconfigurable architectures with the steady growth in the range of FPGA based applications. However, traditional FPGA architecture design methods require time consuming CAD experimentations to identify the most suitable hardware configuration for the target application. Several analytical models have been recently proposed to predict the relative performance of a given set of architectures. Replacing CAD experiments with these analytical models poses as the solution for reducing the complexity of architecture evaluation process. However, among a large set of existing models, an analytical energy model is missing to supplement the architecture evaluation. We argue that energy can be defined as a function of routed wire length and critical path delay. Therefore, we inherit wire length and critical path delay models to derive an analytical energy model for homogeneous FPGA architectures. We evaluate the impact of variations in logic architecture parameters in terms of LUT size, cluster size and inputs per CLB on the energy performance, and show that our energy model accurately captures the trends observed through CAD experiments. An energy model is robust only if its predictions are in agreement with any CAD flow or benchmark suite. We study the robustness of our energy model by varying the seed selection process of placement, optimization goal of clustering and placement, and the nature of the benchmark suite. In all our experimental evaluations, we observe that the energy model accurately captures the performance trends with a high degree of fidelity.

UR - http://www.scopus.com/inward/record.url?scp=84857213036&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84857213036&partnerID=8YFLogxK

U2 - 10.1109/FPT.2011.6132683

DO - 10.1109/FPT.2011.6132683

M3 - Conference contribution

SN - 9781457717406

BT - 2011 International Conference on Field-Programmable Technology, FPT 2011

ER -