An analytical model for evaluating static power of homogeneous FPGA architectures

Yoon Kah Leow, Ali Akoglu, Susan Lysecky

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching the dynamic power in submicron devices. In this article, we propose an analytical model for relating homogeneous island-style-based FPGA architecture to static power. Current FPGA power models are tightly coupled with CAD tools. Our CAD-independent model captures the static power for a given FPGA architecture based on estimates of routing and logic resource utilizations from a pre-technology mapped netlist. We observe an average correlation ratio (C-Ratio) of 95% and a minimum absolute percentage error (MAPE) rate of 15% with respect to the experimental results generated by the Versatile Placement Routing (VPR) tool over the MCNC benchmarks. Our model offers application engineers and FPGA architects the capability to evaluate the impact of their design choices on static power without having to go through CAD-intensive investigations.

Original languageEnglish (US)
Article number18
JournalACM Transactions on Reconfigurable Technology and Systems
Volume6
Issue number4
DOIs
StatePublished - Dec 2013

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Field programmable gate arrays (FPGA)
Analytical models
Computer aided design
Engineers

Keywords

  • Analytical modeling
  • Homogeneous
  • Static power

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

An analytical model for evaluating static power of homogeneous FPGA architectures. / Leow, Yoon Kah; Akoglu, Ali; Lysecky, Susan.

In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 6, No. 4, 18, 12.2013.

Research output: Contribution to journalArticle

@article{ffb95d2d06c64ee6bd407f7065230de4,
title = "An analytical model for evaluating static power of homogeneous FPGA architectures",
abstract = "As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching the dynamic power in submicron devices. In this article, we propose an analytical model for relating homogeneous island-style-based FPGA architecture to static power. Current FPGA power models are tightly coupled with CAD tools. Our CAD-independent model captures the static power for a given FPGA architecture based on estimates of routing and logic resource utilizations from a pre-technology mapped netlist. We observe an average correlation ratio (C-Ratio) of 95{\%} and a minimum absolute percentage error (MAPE) rate of 15{\%} with respect to the experimental results generated by the Versatile Placement Routing (VPR) tool over the MCNC benchmarks. Our model offers application engineers and FPGA architects the capability to evaluate the impact of their design choices on static power without having to go through CAD-intensive investigations.",
keywords = "Analytical modeling, Homogeneous, Static power",
author = "Leow, {Yoon Kah} and Ali Akoglu and Susan Lysecky",
year = "2013",
month = "12",
doi = "10.1145/2535935",
language = "English (US)",
volume = "6",
journal = "ACM Transactions on Reconfigurable Technology and Systems",
issn = "1936-7406",
publisher = "Association for Computing Machinery (ACM)",
number = "4",

}

TY - JOUR

T1 - An analytical model for evaluating static power of homogeneous FPGA architectures

AU - Leow, Yoon Kah

AU - Akoglu, Ali

AU - Lysecky, Susan

PY - 2013/12

Y1 - 2013/12

N2 - As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching the dynamic power in submicron devices. In this article, we propose an analytical model for relating homogeneous island-style-based FPGA architecture to static power. Current FPGA power models are tightly coupled with CAD tools. Our CAD-independent model captures the static power for a given FPGA architecture based on estimates of routing and logic resource utilizations from a pre-technology mapped netlist. We observe an average correlation ratio (C-Ratio) of 95% and a minimum absolute percentage error (MAPE) rate of 15% with respect to the experimental results generated by the Versatile Placement Routing (VPR) tool over the MCNC benchmarks. Our model offers application engineers and FPGA architects the capability to evaluate the impact of their design choices on static power without having to go through CAD-intensive investigations.

AB - As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching the dynamic power in submicron devices. In this article, we propose an analytical model for relating homogeneous island-style-based FPGA architecture to static power. Current FPGA power models are tightly coupled with CAD tools. Our CAD-independent model captures the static power for a given FPGA architecture based on estimates of routing and logic resource utilizations from a pre-technology mapped netlist. We observe an average correlation ratio (C-Ratio) of 95% and a minimum absolute percentage error (MAPE) rate of 15% with respect to the experimental results generated by the Versatile Placement Routing (VPR) tool over the MCNC benchmarks. Our model offers application engineers and FPGA architects the capability to evaluate the impact of their design choices on static power without having to go through CAD-intensive investigations.

KW - Analytical modeling

KW - Homogeneous

KW - Static power

UR - http://www.scopus.com/inward/record.url?scp=84891816639&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84891816639&partnerID=8YFLogxK

U2 - 10.1145/2535935

DO - 10.1145/2535935

M3 - Article

VL - 6

JO - ACM Transactions on Reconfigurable Technology and Systems

JF - ACM Transactions on Reconfigurable Technology and Systems

SN - 1936-7406

IS - 4

M1 - 18

ER -