An efficient combinationality check technique for the synthesis of cyclic combinational circuits

Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Meiling Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

It has been recently pointed out that cyclic circuits are not necessarily sequential, and cyclic topologies that are combinational generally have lower literal counts than their acyclic counterparts. However, the synthesis of cyclic combinational circuits is potentially expensive due to the need to explore a wide range of cyclic topologies and check each of them for combinationality. We first obtain the acyclic implementation of the given set of boolean functions. Then using a branch-and-bound heuristic, we generate cyclic circuits that are to be checked for combinationality. Unlike earlier complex methods for combinationality check, our approach is to check whether this cyclic circuit is functionally equivalent to the acyclic circuit obtained earlier. While synthesizing cyclic circuits with the proposed method, we observed up to 45% improvements in the literal count (for Espresso and LGsynth93 benchmarks) over the acyclic circuit synthesized by the Berkeley sis package.

Original languageEnglish (US)
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages212-215
Number of pages4
Volume1
StatePublished - 2005
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: Jan 18 2005Jan 21 2005

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period1/18/051/21/05

Fingerprint

Combinatorial circuits
Networks (circuits)
Topology
Boolean functions

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Agarwal, V., Kankani, N., Rao, R., Bhardwaj, S., & Wang, M. (2005). An efficient combinationality check technique for the synthesis of cyclic combinational circuits. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 1, pp. 212-215). [1466160]

An efficient combinationality check technique for the synthesis of cyclic combinational circuits. / Agarwal, Vineet; Kankani, Navneeth; Rao, Ravishankar; Bhardwaj, Sarvesh; Wang, Meiling.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1 2005. p. 212-215 1466160.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Agarwal, V, Kankani, N, Rao, R, Bhardwaj, S & Wang, M 2005, An efficient combinationality check technique for the synthesis of cyclic combinational circuits. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. vol. 1, 1466160, pp. 212-215, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 1/18/05.
Agarwal V, Kankani N, Rao R, Bhardwaj S, Wang M. An efficient combinationality check technique for the synthesis of cyclic combinational circuits. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1. 2005. p. 212-215. 1466160
Agarwal, Vineet ; Kankani, Navneeth ; Rao, Ravishankar ; Bhardwaj, Sarvesh ; Wang, Meiling. / An efficient combinationality check technique for the synthesis of cyclic combinational circuits. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1 2005. pp. 212-215
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