An information theoretical framework for analysis and design of nanoscale fault-tolerant memories based on low-density parity-check codes

Bane Vasic, Shashi Kiran Chilappagari

Research output: Contribution to journalArticle

49 Scopus citations

Abstract

In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant memory architectures. Our approach is a modification of the method developed by Taylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzero computational (storage) capacity, i.e., the redundancy necessary to ensure reliability grows asymptotically linearly with the memory size. The restoration phase in the TK method is based on low-density parity-check codes which can be decoded using low complexity decoders. The equivalence of the restoration phase in the TK method and faulty Gallager B algorithm enabled us to establish a theoretical framework for solving problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade.

Original languageEnglish (US)
Pages (from-to)2438-2446
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume54
Issue number11 SPEC. ISS.
DOIs
StatePublished - Dec 1 2007

Keywords

  • Faulty gates
  • Low-density parity-check (LDPC) codes
  • Message passing
  • Reliable storage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'An information theoretical framework for analysis and design of nanoscale fault-tolerant memories based on low-density parity-check codes'. Together they form a unique fingerprint.

  • Cite this