An optical interconnection network and a modified snooping protocol for the design of large-scale symmetric multiprocessors (SMPs)

Ahmed Louri, Avinash Karanth Kodi

Research output: Contribution to journalArticle

9 Scopus citations

Abstract

In Symmetric Multiprocessors (SMPs), the cache coherence overhead and the speed of the shared buses limit the address/snoop bandwidth needed to broadcast transactions to all processors. As a solution, a scalable address subnetwork called Symmetric Multiprocessor Network (SYMNET) is proposed in which address requests and snoop responses of SMPs are implemented optically. SYMNET not only uses passive optical interconnects that increases the speed of the proposed network, but also pipelines address requests at a much faster rate than electronics. This increases the address bandwidth for snooping, but the preservation of cache coherence can no longer be maintained with the usual snooping protocols. A modified coherence protocol, Coherence in SYMNET (COSYM), is introduced to solve the coherence problem. COSYM was evaluated with a subset of Splash-2 benchmarks and compared with the electrical bus-based MOESI protocol. The simulation studies have shown a 5-66 percent improvement in execution time for COSYM as compared to MOESI for various applications. Simulations have also shown that the average latency for a transaction to complete using COSYM protocol was 5-78 percent better than the MOESI protocol. It is also seen that SYMNET can scale up to hundreds of processors while still using fast snooping-based cache coherence protocols, and additional performance gains may be attained with further improvement in optical device technology.

Original languageEnglish (US)
Pages (from-to)1093-1104
Number of pages12
JournalIEEE Transactions on Parallel and Distributed Systems
Volume15
Issue number12
DOIs
StatePublished - Dec 1 2004

Keywords

  • Cache coherence
  • Parallel optical interconnects
  • SMPs
  • Scalable optical networks

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Computational Theory and Mathematics

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