Analysis and Design of Finite Alphabet Iterative Decoders Robust to Faulty Hardware

Elsa Dupraz, David Declercq, Bane V Vasic, Valentin Savin

Research output: Contribution to journalArticle

14 Scopus citations

Abstract

This paper addresses the problem of designing low-density parity check decoders robust to transient errors introduced by faulty hardware. We assume that the faulty hardware introduces errors during the message-passing updates, and we propose a general framework for the definition of the message update faulty functions. Within this framework, we define symmetry conditions for the faulty functions and derive two simple error models used in the analysis. With this analysis, we propose a new interpretation of the functional density evolution threshold introduced by Kameni et al. in the recent literature and show its limitations in the case of highly unreliable hardware. However, we show that under restricted decoder noise conditions, the functional threshold can be used to predict the convergence behavior of finite alphabet iterative decoders (FAIDs) under faulty hardware. In particular, we reveal the existence of robust and nonrobust FAIDs and propose a framework for the design of robust decoders. We finally illustrate robust-and nonrobust-decoder behaviors of finite-length codes using Monte Carlo simulations.

Original languageEnglish (US)
Article number7147804
Pages (from-to)2797-2809
Number of pages13
JournalIEEE Transactions on Communications
Volume63
Issue number8
DOIs
Publication statusPublished - Aug 1 2015

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Keywords

  • Block codes
  • Decoding
  • Error correction
  • Fault tolerance

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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