Analysis of one-step majority logic decoding under correlated data-dependent gate failures

Srdan Brkic, Predrag Ivanis, Bane V Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

In this paper we present analysis of one-step majority logic decoders made of unreliable components in the presence of data-dependent gate failures. Gate failures are modeled by a Markov chain, and based on the combinatorial representation of the fault configurations, a closed-form expression for the average bit error rate is derived for a regular LDPC code ensemble. Presented analysis framework is then used for obtaining upper bounds on decoding performance under timing errors.

Original languageEnglish (US)
Title of host publicationIEEE International Symposium on Information Theory - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2599-2603
Number of pages5
ISBN (Print)9781479951864
DOIs
Publication statusPublished - 2014
Event2014 IEEE International Symposium on Information Theory, ISIT 2014 - Honolulu, HI, United States
Duration: Jun 29 2014Jul 4 2014

Other

Other2014 IEEE International Symposium on Information Theory, ISIT 2014
CountryUnited States
CityHonolulu, HI
Period6/29/147/4/14

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ASJC Scopus subject areas

  • Applied Mathematics
  • Modeling and Simulation
  • Theoretical Computer Science
  • Information Systems

Cite this

Brkic, S., Ivanis, P., & Vasic, B. V. (2014). Analysis of one-step majority logic decoding under correlated data-dependent gate failures. In IEEE International Symposium on Information Theory - Proceedings (pp. 2599-2603). [6875304] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISIT.2014.6875304