Analysis of Taylor-Kuznetsov memory using one-step majority logic decoder

Elsa Dupraz, David Declercq, Bane V Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


This paper addresses the problem of constructing reliable memories from unreliable components. We consider the memory construction proposed by Taylor in which a codeword stored in a faulty memory is regularly updated by an LDPC decoder to overcome the memory degradation. We assume that the LDPC decoder used in the system is a faulty one-step majority logic decoder. Compared to [1], [2] which analyze only the faulty one-step majority logic decoder, we analyze here the reliability of the whole memory construction. We introduce a sequence of output errors probabilities at successive time instants and determine the properties and the fixed points of the sequence. From the fixed-point analysis, we define a threshold that predicts the noise level which can be tolerated for the memory to stay reliable. We finally represent the reliability regions of the Taylor-Kuznetsov memory with respect to the decoder noise parameters and validate the theoretical results with Monte-Carlo simulations.

Original languageEnglish (US)
Title of host publication2015 Information Theory and Applications Workshop, ITA 2015 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages8
ISBN (Print)9781479971954
StatePublished - Oct 27 2015
EventInformation Theory and Applications Workshop, ITA 2015 - San Diego, United States
Duration: Feb 1 2015Feb 6 2015


OtherInformation Theory and Applications Workshop, ITA 2015
Country/TerritoryUnited States
CitySan Diego


  • Decoding
  • Degradation
  • Error probability
  • Memory architecture
  • Noise
  • Parity check codes
  • Reliability

ASJC Scopus subject areas

  • Computer Science Applications
  • Information Systems


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