Analytical performance of one-step majority logic decoding of regular LDPC codes

Rathnakumar Radhakrishnan, Sundararajan Sankaranarayanan, Bane V Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In this paper, we present a combinatorial algorithm to calculate the exact bit error rate performance of regular low-density parity check codes under one-step majority logic decoding. Majority logic decoders have regained importance in nano-scale memories due to their resilience to both memory and logic gate failures. This result is an extension of the work of Rudolph on error correction capability of majority-logic decoders.

Original languageEnglish (US)
Title of host publicationIEEE International Symposium on Information Theory - Proceedings
Pages231-235
Number of pages5
DOIs
StatePublished - 2007
Event2007 IEEE International Symposium on Information Theory, ISIT 2007 - Nice, France
Duration: Jun 24 2007Jun 29 2007

Other

Other2007 IEEE International Symposium on Information Theory, ISIT 2007
CountryFrance
CityNice
Period6/24/076/29/07

Fingerprint

Majority logic
Decoding
Data storage equipment
Logic gates
Error correction
Bit error rate

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Radhakrishnan, R., Sankaranarayanan, S., & Vasic, B. V. (2007). Analytical performance of one-step majority logic decoding of regular LDPC codes. In IEEE International Symposium on Information Theory - Proceedings (pp. 231-235). [4557231] https://doi.org/10.1109/ISIT.2007.4557231

Analytical performance of one-step majority logic decoding of regular LDPC codes. / Radhakrishnan, Rathnakumar; Sankaranarayanan, Sundararajan; Vasic, Bane V.

IEEE International Symposium on Information Theory - Proceedings. 2007. p. 231-235 4557231.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Radhakrishnan, R, Sankaranarayanan, S & Vasic, BV 2007, Analytical performance of one-step majority logic decoding of regular LDPC codes. in IEEE International Symposium on Information Theory - Proceedings., 4557231, pp. 231-235, 2007 IEEE International Symposium on Information Theory, ISIT 2007, Nice, France, 6/24/07. https://doi.org/10.1109/ISIT.2007.4557231
Radhakrishnan R, Sankaranarayanan S, Vasic BV. Analytical performance of one-step majority logic decoding of regular LDPC codes. In IEEE International Symposium on Information Theory - Proceedings. 2007. p. 231-235. 4557231 https://doi.org/10.1109/ISIT.2007.4557231
Radhakrishnan, Rathnakumar ; Sankaranarayanan, Sundararajan ; Vasic, Bane V. / Analytical performance of one-step majority logic decoding of regular LDPC codes. IEEE International Symposium on Information Theory - Proceedings. 2007. pp. 231-235
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