Analytical performance of one-step majority logic decoding of regular LDPC codes

Rathnakumar Radhakrishnan, Sundararajan Sankaranarayanan, Bane Vasić

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this paper, we present a combinatorial algorithm to calculate the exact bit error rate performance of regular low-density parity check codes under one-step majority logic decoding. Majority logic decoders have regained importance in nano-scale memories due to their resilience to both memory and logic gate failures. This result is an extension of the work of Rudolph on error correction capability of majority-logic decoders.

Original languageEnglish (US)
Title of host publicationProceedings - 2007 IEEE International Symposium on Information Theory, ISIT 2007
Pages231-235
Number of pages5
DOIs
StatePublished - Dec 1 2007
Event2007 IEEE International Symposium on Information Theory, ISIT 2007 - Nice, France
Duration: Jun 24 2007Jun 29 2007

Publication series

NameIEEE International Symposium on Information Theory - Proceedings
ISSN (Print)2157-8101

Other

Other2007 IEEE International Symposium on Information Theory, ISIT 2007
CountryFrance
CityNice
Period6/24/076/29/07

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Modeling and Simulation
  • Applied Mathematics

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    Radhakrishnan, R., Sankaranarayanan, S., & Vasić, B. (2007). Analytical performance of one-step majority logic decoding of regular LDPC codes. In Proceedings - 2007 IEEE International Symposium on Information Theory, ISIT 2007 (pp. 231-235). [4557231] (IEEE International Symposium on Information Theory - Proceedings). https://doi.org/10.1109/ISIT.2007.4557231