Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing

Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David K Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, Ikuo Miyoshi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

39 Citations (Scopus)

Abstract

A key challenge in next-generation supercomputing is to effectively schedule limited power resources. Modern processors suffer from increasingly large power variations due to the chip manufacturing process. These variations lead to power inhomogeneity in current systems and manifest into performance inhomogeneity in power constrained environments, drastically limiting supercomputing performance. We present a first-of-its-kind study on manufacturing variability on four production HPC systems spanning four microarchitectures, analyze its impact on HPC applications, and propose a novel variation-aware power budgeting scheme to maximize effective application performance. Our low-cost and scalable budgeting algorithm strives to achieve performance homogeneity under a power constraint by deriving application-specific, module-level power allocations. Experimental results using a 1,920 socket system show up to 5.4X speedup, with an average speedup of 1.8X across all benchmarks when compared to a variation-unaware power allocation scheme.

Original languageEnglish (US)
Title of host publicationInternational Conference for High Performance Computing, Networking, Storage and Analysis, SC
PublisherIEEE Computer Society
Volume15-20-November-2015
ISBN (Print)9781450337236
DOIs
StatePublished - Nov 15 2015
EventInternational Conference for High Performance Computing, Networking, Storage and Analysis, SC 2015 - Austin, United States
Duration: Nov 15 2015Nov 20 2015

Other

OtherInternational Conference for High Performance Computing, Networking, Storage and Analysis, SC 2015
CountryUnited States
CityAustin
Period11/15/1511/20/15

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Keywords

  • performance modeling
  • power-constrained HPC

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture
  • Software

Cite this

Inadomi, Y., Patki, T., Inoue, K., Aoyagi, M., Rountree, B., Schulz, M., ... Miyoshi, I. (2015). Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing. In International Conference for High Performance Computing, Networking, Storage and Analysis, SC (Vol. 15-20-November-2015). [a78] IEEE Computer Society. https://doi.org/10.1145/2807591.2807638

Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing. / Inadomi, Yuichi; Patki, Tapasya; Inoue, Koji; Aoyagi, Mutsumi; Rountree, Barry; Schulz, Martin; Lowenthal, David K; Wada, Yasutaka; Fukazawa, Keiichiro; Ueda, Masatsugu; Kondo, Masaaki; Miyoshi, Ikuo.

International Conference for High Performance Computing, Networking, Storage and Analysis, SC. Vol. 15-20-November-2015 IEEE Computer Society, 2015. a78.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Inadomi, Y, Patki, T, Inoue, K, Aoyagi, M, Rountree, B, Schulz, M, Lowenthal, DK, Wada, Y, Fukazawa, K, Ueda, M, Kondo, M & Miyoshi, I 2015, Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing. in International Conference for High Performance Computing, Networking, Storage and Analysis, SC. vol. 15-20-November-2015, a78, IEEE Computer Society, International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2015, Austin, United States, 11/15/15. https://doi.org/10.1145/2807591.2807638
Inadomi Y, Patki T, Inoue K, Aoyagi M, Rountree B, Schulz M et al. Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing. In International Conference for High Performance Computing, Networking, Storage and Analysis, SC. Vol. 15-20-November-2015. IEEE Computer Society. 2015. a78 https://doi.org/10.1145/2807591.2807638
Inadomi, Yuichi ; Patki, Tapasya ; Inoue, Koji ; Aoyagi, Mutsumi ; Rountree, Barry ; Schulz, Martin ; Lowenthal, David K ; Wada, Yasutaka ; Fukazawa, Keiichiro ; Ueda, Masatsugu ; Kondo, Masaaki ; Miyoshi, Ikuo. / Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing. International Conference for High Performance Computing, Networking, Storage and Analysis, SC. Vol. 15-20-November-2015 IEEE Computer Society, 2015.
@inproceedings{827248cb5d1a4904a00957de3f8f66f0,
title = "Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing",
abstract = "A key challenge in next-generation supercomputing is to effectively schedule limited power resources. Modern processors suffer from increasingly large power variations due to the chip manufacturing process. These variations lead to power inhomogeneity in current systems and manifest into performance inhomogeneity in power constrained environments, drastically limiting supercomputing performance. We present a first-of-its-kind study on manufacturing variability on four production HPC systems spanning four microarchitectures, analyze its impact on HPC applications, and propose a novel variation-aware power budgeting scheme to maximize effective application performance. Our low-cost and scalable budgeting algorithm strives to achieve performance homogeneity under a power constraint by deriving application-specific, module-level power allocations. Experimental results using a 1,920 socket system show up to 5.4X speedup, with an average speedup of 1.8X across all benchmarks when compared to a variation-unaware power allocation scheme.",
keywords = "performance modeling, power-constrained HPC",
author = "Yuichi Inadomi and Tapasya Patki and Koji Inoue and Mutsumi Aoyagi and Barry Rountree and Martin Schulz and Lowenthal, {David K} and Yasutaka Wada and Keiichiro Fukazawa and Masatsugu Ueda and Masaaki Kondo and Ikuo Miyoshi",
year = "2015",
month = "11",
day = "15",
doi = "10.1145/2807591.2807638",
language = "English (US)",
isbn = "9781450337236",
volume = "15-20-November-2015",
booktitle = "International Conference for High Performance Computing, Networking, Storage and Analysis, SC",
publisher = "IEEE Computer Society",

}

TY - GEN

T1 - Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing

AU - Inadomi, Yuichi

AU - Patki, Tapasya

AU - Inoue, Koji

AU - Aoyagi, Mutsumi

AU - Rountree, Barry

AU - Schulz, Martin

AU - Lowenthal, David K

AU - Wada, Yasutaka

AU - Fukazawa, Keiichiro

AU - Ueda, Masatsugu

AU - Kondo, Masaaki

AU - Miyoshi, Ikuo

PY - 2015/11/15

Y1 - 2015/11/15

N2 - A key challenge in next-generation supercomputing is to effectively schedule limited power resources. Modern processors suffer from increasingly large power variations due to the chip manufacturing process. These variations lead to power inhomogeneity in current systems and manifest into performance inhomogeneity in power constrained environments, drastically limiting supercomputing performance. We present a first-of-its-kind study on manufacturing variability on four production HPC systems spanning four microarchitectures, analyze its impact on HPC applications, and propose a novel variation-aware power budgeting scheme to maximize effective application performance. Our low-cost and scalable budgeting algorithm strives to achieve performance homogeneity under a power constraint by deriving application-specific, module-level power allocations. Experimental results using a 1,920 socket system show up to 5.4X speedup, with an average speedup of 1.8X across all benchmarks when compared to a variation-unaware power allocation scheme.

AB - A key challenge in next-generation supercomputing is to effectively schedule limited power resources. Modern processors suffer from increasingly large power variations due to the chip manufacturing process. These variations lead to power inhomogeneity in current systems and manifest into performance inhomogeneity in power constrained environments, drastically limiting supercomputing performance. We present a first-of-its-kind study on manufacturing variability on four production HPC systems spanning four microarchitectures, analyze its impact on HPC applications, and propose a novel variation-aware power budgeting scheme to maximize effective application performance. Our low-cost and scalable budgeting algorithm strives to achieve performance homogeneity under a power constraint by deriving application-specific, module-level power allocations. Experimental results using a 1,920 socket system show up to 5.4X speedup, with an average speedup of 1.8X across all benchmarks when compared to a variation-unaware power allocation scheme.

KW - performance modeling

KW - power-constrained HPC

UR - http://www.scopus.com/inward/record.url?scp=84966687194&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84966687194&partnerID=8YFLogxK

U2 - 10.1145/2807591.2807638

DO - 10.1145/2807591.2807638

M3 - Conference contribution

SN - 9781450337236

VL - 15-20-November-2015

BT - International Conference for High Performance Computing, Networking, Storage and Analysis, SC

PB - IEEE Computer Society

ER -