Application specific low power hybrid FPGA architecture design

Ali Akoglu, Aravind Dasu, Sethuraman Panchanathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Increasing demand for configuration time aware processing with stringent constraints for flexibility necessitates the design and development of a dynamically fast reconfigurable processor. This research work presents results obtained from hybrid FPGA architecture design methodology proposed in earlier work. Hybrid architecture is formed of ASIC units and LUT based processing elements. ASIC units represent tasks or core clusters obtained through common sub-graph analysis between basic blocks within and across routines of computation intensive applications and are basically recurring patterns. Results show that partial reconfiguration with the use of computation cores embedded in a sea of LUTs offer potential for massive savings in gate density by eliminating the need for redundant sub-circuit pattern configurations. Since ASICs cover only parts of data flow graphs, remaining computations are implemented on LUT based reconfigurable hardware. A new packing algorithm is proposed to form LUT based processing elements. Packing cost function prioritizes reduction of input/output pins of the clusters being formed. Results show that significant savings in number of nets to be routed are obtained through proposed method.

Original languageEnglish (US)
Title of host publicationProceedings of SPIE - The International Society for Optical Engineering
EditorsS. Sudharsanan, V.M. Bove, Jr.
Pages21-31
Number of pages11
Volume5683
DOIs
StatePublished - 2005
EventProceedings of SPIE-IS and T Electronic Imaging - Embedded Processors for Multimedia and Communications II - San Jose, CA, United States
Duration: Jan 17 2005Jan 18 2005

Other

OtherProceedings of SPIE-IS and T Electronic Imaging - Embedded Processors for Multimedia and Communications II
CountryUnited States
CitySan Jose, CA
Period1/17/051/18/05

Fingerprint

application specific integrated circuits
Application specific integrated circuits
Field programmable gate arrays (FPGA)
flow graphs
reconfigurable hardware
Processing
Data flow graphs
Reconfigurable hardware
configurations
Cost functions
central processing units
flexibility
methodology
costs
Networks (circuits)
output

Keywords

  • FPGA
  • Hybrid
  • Packing
  • Reconfigurable architecture

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

Akoglu, A., Dasu, A., & Panchanathan, S. (2005). Application specific low power hybrid FPGA architecture design. In S. Sudharsanan, & V. M. Bove, Jr. (Eds.), Proceedings of SPIE - The International Society for Optical Engineering (Vol. 5683, pp. 21-31). [03] https://doi.org/10.1117/12.593286

Application specific low power hybrid FPGA architecture design. / Akoglu, Ali; Dasu, Aravind; Panchanathan, Sethuraman.

Proceedings of SPIE - The International Society for Optical Engineering. ed. / S. Sudharsanan; V.M. Bove, Jr. Vol. 5683 2005. p. 21-31 03.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Akoglu, A, Dasu, A & Panchanathan, S 2005, Application specific low power hybrid FPGA architecture design. in S Sudharsanan & VM Bove, Jr. (eds), Proceedings of SPIE - The International Society for Optical Engineering. vol. 5683, 03, pp. 21-31, Proceedings of SPIE-IS and T Electronic Imaging - Embedded Processors for Multimedia and Communications II, San Jose, CA, United States, 1/17/05. https://doi.org/10.1117/12.593286
Akoglu A, Dasu A, Panchanathan S. Application specific low power hybrid FPGA architecture design. In Sudharsanan S, Bove, Jr. VM, editors, Proceedings of SPIE - The International Society for Optical Engineering. Vol. 5683. 2005. p. 21-31. 03 https://doi.org/10.1117/12.593286
Akoglu, Ali ; Dasu, Aravind ; Panchanathan, Sethuraman. / Application specific low power hybrid FPGA architecture design. Proceedings of SPIE - The International Society for Optical Engineering. editor / S. Sudharsanan ; V.M. Bove, Jr. Vol. 5683 2005. pp. 21-31
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