### Abstract

In a circuit, timing errors occur when a logic gate output does not switch before the clock rising edge. In this letter, we consider Gallager B decoders under timing errors, following the error model derived by Amaricai et al. from SPICE measurements. For this model, we provide a theoretical analysis of the performance of LDPC decoders. This letter is based on the analysis of the computation trees of the decoder free of logic gate errors and of the decoder with timing errors. As a main result, we show that as the number of iterations goes to infinity, the error probability of the decoder with timing errors converges to the error probability of the logic gate error-free decoder. Monte Carlo simulations confirm this result even for moderate code lengths, which is in accordance with the experimental observations.

Language | English (US) |
---|---|

Article number | 7805222 |

Pages | 698-701 |

Number of pages | 4 |

Journal | IEEE Communications Letters |

Volume | 21 |

Issue number | 4 |

DOIs | |

State | Published - Apr 1 2017 |

### Fingerprint

### Keywords

- computation trees
- faulty Gallager B decoders
- Low-density parity check codes
- timing errors

### ASJC Scopus subject areas

- Modeling and Simulation
- Computer Science Applications
- Electrical and Electronic Engineering

### Cite this

*IEEE Communications Letters*,

*21*(4), 698-701. [7805222]. DOI: 10.1109/LCOMM.2017.2647804

**Asymptotic error probability of the Gallager B decoder under timing errors.** / Dupraz, Elsa; Declercq, David; Vasic, Bane.

Research output: Contribution to journal › Article

*IEEE Communications Letters*, vol 21, no. 4, 7805222, pp. 698-701. DOI: 10.1109/LCOMM.2017.2647804

}

TY - JOUR

T1 - Asymptotic error probability of the Gallager B decoder under timing errors

AU - Dupraz,Elsa

AU - Declercq,David

AU - Vasic,Bane

PY - 2017/4/1

Y1 - 2017/4/1

N2 - In a circuit, timing errors occur when a logic gate output does not switch before the clock rising edge. In this letter, we consider Gallager B decoders under timing errors, following the error model derived by Amaricai et al. from SPICE measurements. For this model, we provide a theoretical analysis of the performance of LDPC decoders. This letter is based on the analysis of the computation trees of the decoder free of logic gate errors and of the decoder with timing errors. As a main result, we show that as the number of iterations goes to infinity, the error probability of the decoder with timing errors converges to the error probability of the logic gate error-free decoder. Monte Carlo simulations confirm this result even for moderate code lengths, which is in accordance with the experimental observations.

AB - In a circuit, timing errors occur when a logic gate output does not switch before the clock rising edge. In this letter, we consider Gallager B decoders under timing errors, following the error model derived by Amaricai et al. from SPICE measurements. For this model, we provide a theoretical analysis of the performance of LDPC decoders. This letter is based on the analysis of the computation trees of the decoder free of logic gate errors and of the decoder with timing errors. As a main result, we show that as the number of iterations goes to infinity, the error probability of the decoder with timing errors converges to the error probability of the logic gate error-free decoder. Monte Carlo simulations confirm this result even for moderate code lengths, which is in accordance with the experimental observations.

KW - computation trees

KW - faulty Gallager B decoders

KW - Low-density parity check codes

KW - timing errors

UR - http://www.scopus.com/inward/record.url?scp=85018167482&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85018167482&partnerID=8YFLogxK

U2 - 10.1109/LCOMM.2017.2647804

DO - 10.1109/LCOMM.2017.2647804

M3 - Article

VL - 21

SP - 698

EP - 701

JO - IEEE Communications Letters

T2 - IEEE Communications Letters

JF - IEEE Communications Letters

SN - 1089-7798

IS - 4

M1 - 7805222

ER -