Automatic extraction of requirements from state-based hardware designs for runtime verification

Minjun Seo, Roman Lysecky

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Runtime monitoring and verification enables a system to monitor itself and ensure system requirements are met even in the presence of dynamic environments. For hardware, state-based models are widely used, but verifying the correctness between the state-based model and hardware implementation is time-consuming and difficult. This paper presents a novel method for extracting hardware verification requirements from state-based hardware models to construct a hierarchical runtime monitoring graph that can be efficiently used at runtime to verify correctness.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2019 - Proceedings of the 2019 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages295-298
Number of pages4
ISBN (Electronic)9781450362528
DOIs
StatePublished - May 13 2019
Event29th Great Lakes Symposium on VLSI, GLSVLSI 2019 - Tysons Corner, United States
Duration: May 9 2019May 11 2019

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference29th Great Lakes Symposium on VLSI, GLSVLSI 2019
CountryUnited States
CityTysons Corner
Period5/9/195/11/19

Keywords

  • Formal requirements models
  • Hardware-based observations
  • Periodic statement machines
  • Runtime verification

ASJC Scopus subject areas

  • Engineering(all)

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