Beyond DVFS: A first look at performance under a hardware-enforced power bound

Barry Rountree, Dong H. Ahn, Bronis R. De Supinski, David K. Lowenthal, Martin Schulz

Research output: Chapter in Book/Report/Conference proceedingConference contribution

102 Scopus citations

Abstract

Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel's Sandy Bridge family of processors, researchers now have a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment and detail both the opportunities and potential pitfalls of using this technique to control processor power. As part of this evaluation we measure power and performance for single-processor instances of several of the NAS Parallel Benchmarks. Additionally, we focus on the behavior of a single benchmark, MG, under several different power bounds. We quantify the well-known manufacturing variation in processor power efficiency and show that, in the absence of a power bound, this variation has no correlation to performance. We then show that execution under a power bound translates this variation in efficiency into variation in performance.

Original languageEnglish (US)
Title of host publicationProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
Pages947-953
Number of pages7
DOIs
StatePublished - Oct 18 2012
Event2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012 - Shanghai, China
Duration: May 21 2012May 25 2012

Publication series

NameProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012

Other

Other2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
CountryChina
CityShanghai
Period5/21/125/25/12

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Keywords

  • Power bound
  • RAPL

ASJC Scopus subject areas

  • Software

Cite this

Rountree, B., Ahn, D. H., De Supinski, B. R., Lowenthal, D. K., & Schulz, M. (2012). Beyond DVFS: A first look at performance under a hardware-enforced power bound. In Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012 (pp. 947-953). [6270741] (Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012). https://doi.org/10.1109/IPDPSW.2012.116