Bit-by-bit pipelined and hybrid-grained 2d architecture for motion estimation of H.264/AVC

Yang Song, Ali Akoglu

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

In H.264/AVC, the motion estimation (ME) routine supports variable block size and involves highly parallel sum of absolute difference (SAD) computations. In this study, we introduce a bit serial hybrid-grained processing element (PE) based 2D architecture that has both early termination and intensive data reuse capabilities. PEs operate on most significant bit-first arithmetic for early termination and the 2D architecture enables on-chip data reuse between neighboring PEs in a bit-by-bit pipelined fashion. Hybrid-grained PEs reduce the hardware overhead of conventional adder tree structures used for implementing the variable block size ME. Our design reduces the gate count by 7x compared to its ASIC counterpart, operates at a comparable frequency while sustaining 30 fps and 60 fps; and outperforms bit parallel and bit serial architectures in terms of throughput and performance per gate for various video formats.

Original languageEnglish (US)
Pages (from-to)49-62
Number of pages14
JournalJournal of Signal Processing Systems
Volume68
Issue number1
DOIs
StatePublished - Jul 1 2012

Keywords

  • Bit parallel
  • Bit serial
  • Early termination
  • Full search
  • H.264/AVC
  • Hybrid-grained
  • Motion estimation
  • Variable block size

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Theoretical Computer Science
  • Signal Processing
  • Information Systems
  • Modeling and Simulation
  • Hardware and Architecture

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