Building a robust software-based router using network processors

Tammo Spalink, Scott Karlin, Larry Lee Peterson, Yitzchak Gottlieb

Research output: Chapter in Book/Report/Conference proceedingChapter

98 Citations (Scopus)

Abstract

Recent efforts to add new services to the Internet have increased interest in software-based routers that are easy to extend and evolve. This paper describes our experiences using emerging network processors - in particular, the Intel IXP1200 - to implement a router. We show it is possible to combine an IXP1200 development board and a PC to build an inexpensive router that forwards minimum-sized packets at a rate of 3,47Mpps. This is nearly an order of magnitude faster than existing pure PC-based routers, and sufficient to support 1.77Gbps of aggregate link bandwidth. At lesser aggregate line speeds, our design also allows the excess resources available on the IXP1200 to be used robustly for extra packet processing. For example, with 8 × 100Mbps links, 240 register operations and 96 bytes of state storage are available for each 64-byte packet. Using a hierarchical architecture we can guarantee line-speed forwarding rates for simple packets with the IXP1200, and still have extra capacity to process exceptional packets with the Pentium. Up to 310Kpps of the traffic can be routed through the Pentium to receive 1510 cycles of extra per-packet processing.

Original languageEnglish (US)
Title of host publicationOperating Systems Review (ACM)
Pages216-229
Number of pages14
Volume35
Edition5
DOIs
StatePublished - Dec 2001
Externally publishedYes

Fingerprint

Routers
Processing
Telecommunication links
Internet
Bandwidth

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Spalink, T., Karlin, S., Peterson, L. L., & Gottlieb, Y. (2001). Building a robust software-based router using network processors. In Operating Systems Review (ACM) (5 ed., Vol. 35, pp. 216-229) https://doi.org/10.1145/502059.502056

Building a robust software-based router using network processors. / Spalink, Tammo; Karlin, Scott; Peterson, Larry Lee; Gottlieb, Yitzchak.

Operating Systems Review (ACM). Vol. 35 5. ed. 2001. p. 216-229.

Research output: Chapter in Book/Report/Conference proceedingChapter

Spalink, T, Karlin, S, Peterson, LL & Gottlieb, Y 2001, Building a robust software-based router using network processors. in Operating Systems Review (ACM). 5 edn, vol. 35, pp. 216-229. https://doi.org/10.1145/502059.502056
Spalink T, Karlin S, Peterson LL, Gottlieb Y. Building a robust software-based router using network processors. In Operating Systems Review (ACM). 5 ed. Vol. 35. 2001. p. 216-229 https://doi.org/10.1145/502059.502056
Spalink, Tammo ; Karlin, Scott ; Peterson, Larry Lee ; Gottlieb, Yitzchak. / Building a robust software-based router using network processors. Operating Systems Review (ACM). Vol. 35 5. ed. 2001. pp. 216-229
@inbook{90e5ccdf06f142c694e9d3ba856b5b9a,
title = "Building a robust software-based router using network processors",
abstract = "Recent efforts to add new services to the Internet have increased interest in software-based routers that are easy to extend and evolve. This paper describes our experiences using emerging network processors - in particular, the Intel IXP1200 - to implement a router. We show it is possible to combine an IXP1200 development board and a PC to build an inexpensive router that forwards minimum-sized packets at a rate of 3,47Mpps. This is nearly an order of magnitude faster than existing pure PC-based routers, and sufficient to support 1.77Gbps of aggregate link bandwidth. At lesser aggregate line speeds, our design also allows the excess resources available on the IXP1200 to be used robustly for extra packet processing. For example, with 8 × 100Mbps links, 240 register operations and 96 bytes of state storage are available for each 64-byte packet. Using a hierarchical architecture we can guarantee line-speed forwarding rates for simple packets with the IXP1200, and still have extra capacity to process exceptional packets with the Pentium. Up to 310Kpps of the traffic can be routed through the Pentium to receive 1510 cycles of extra per-packet processing.",
author = "Tammo Spalink and Scott Karlin and Peterson, {Larry Lee} and Yitzchak Gottlieb",
year = "2001",
month = "12",
doi = "10.1145/502059.502056",
language = "English (US)",
volume = "35",
pages = "216--229",
booktitle = "Operating Systems Review (ACM)",
edition = "5",

}

TY - CHAP

T1 - Building a robust software-based router using network processors

AU - Spalink, Tammo

AU - Karlin, Scott

AU - Peterson, Larry Lee

AU - Gottlieb, Yitzchak

PY - 2001/12

Y1 - 2001/12

N2 - Recent efforts to add new services to the Internet have increased interest in software-based routers that are easy to extend and evolve. This paper describes our experiences using emerging network processors - in particular, the Intel IXP1200 - to implement a router. We show it is possible to combine an IXP1200 development board and a PC to build an inexpensive router that forwards minimum-sized packets at a rate of 3,47Mpps. This is nearly an order of magnitude faster than existing pure PC-based routers, and sufficient to support 1.77Gbps of aggregate link bandwidth. At lesser aggregate line speeds, our design also allows the excess resources available on the IXP1200 to be used robustly for extra packet processing. For example, with 8 × 100Mbps links, 240 register operations and 96 bytes of state storage are available for each 64-byte packet. Using a hierarchical architecture we can guarantee line-speed forwarding rates for simple packets with the IXP1200, and still have extra capacity to process exceptional packets with the Pentium. Up to 310Kpps of the traffic can be routed through the Pentium to receive 1510 cycles of extra per-packet processing.

AB - Recent efforts to add new services to the Internet have increased interest in software-based routers that are easy to extend and evolve. This paper describes our experiences using emerging network processors - in particular, the Intel IXP1200 - to implement a router. We show it is possible to combine an IXP1200 development board and a PC to build an inexpensive router that forwards minimum-sized packets at a rate of 3,47Mpps. This is nearly an order of magnitude faster than existing pure PC-based routers, and sufficient to support 1.77Gbps of aggregate link bandwidth. At lesser aggregate line speeds, our design also allows the excess resources available on the IXP1200 to be used robustly for extra packet processing. For example, with 8 × 100Mbps links, 240 register operations and 96 bytes of state storage are available for each 64-byte packet. Using a hierarchical architecture we can guarantee line-speed forwarding rates for simple packets with the IXP1200, and still have extra capacity to process exceptional packets with the Pentium. Up to 310Kpps of the traffic can be routed through the Pentium to receive 1510 cycles of extra per-packet processing.

UR - http://www.scopus.com/inward/record.url?scp=0036038994&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036038994&partnerID=8YFLogxK

U2 - 10.1145/502059.502056

DO - 10.1145/502059.502056

M3 - Chapter

VL - 35

SP - 216

EP - 229

BT - Operating Systems Review (ACM)

ER -