Building extensible routers using network processors

Nadia Shalaby, Andy Bavier, Yitzchak Gottlieb, Scott Karlin, Larry Peterson, Xiaohu Qie, Tammo Spalink, Mike Wawrzoniak

Research output: Contribution to journalArticle

Abstract

This paper describes our effort to build extensible routers using a combination of general-purpose and network processors. We emphasize five overriding challenges that dictate our design decisions: (1) optimal resource allocation; (2) efficient but flexible scheduling of the CPU; (3) maintaining overall router robustness; (4) maximizing router performance; and (5) providing sufficient extensibility to enable the injection of new functionality into the router. We adopt a hierarchical architecture, in which packet flows traverse a range of processing/forwarding paths, thereby partitioning hardware and software in concert. This paper both presents the architecture, and describes our experiences implementing the architecture and addressing the five design challenges in a prototype built from Intel IXP 1200 and a Pentium.

Original languageEnglish (US)
Pages (from-to)1155-1194
Number of pages40
JournalSoftware - Practice and Experience
Volume35
Issue number12
DOIs
StatePublished - Oct 1 2005

Keywords

  • CPU scheduling
  • Extensible router design
  • Hierarchical router architecture
  • Intel IXP 1200
  • Network processors
  • Resource allocation

ASJC Scopus subject areas

  • Software

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  • Cite this

    Shalaby, N., Bavier, A., Gottlieb, Y., Karlin, S., Peterson, L., Qie, X., Spalink, T., & Wawrzoniak, M. (2005). Building extensible routers using network processors. Software - Practice and Experience, 35(12), 1155-1194. https://doi.org/10.1002/spe.667