Buried oxide densification for low power, low voltage CMOS applications

L. P. Allen, M. J. Anc, J. Jiao, B. Guss, Supapan Seraphin, S. T. Liu, W. Jenkins

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The properties of 120 nm BOX (buried oxide) and 360 nm SIMOX (separation by implantation of oxygen) were examined as a function of anneal ramp rate and temperature. The slower ramp rate (1 °C/min) contributed to the reduction of islands within the buried oxide layer. Both the slow ramp rate and high temperature (1350 °C) of anneal decreased the interface roughness of the Si/BOX interface in both materials. Results of the `island free' thin BOX layer showed a 30 V reduction in the threshold voltage shift upon irradiation to 1 Mrad with consistent gate oxide integrity.

Original languageEnglish (US)
Title of host publicationIEEE International SOI Conference
Editors Anon
PublisherIEEE
Pages39-40
Number of pages2
Publication statusPublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International SOI Conference - Stuart, FL, USA
Duration: Oct 5 1998Oct 8 1998

Other

OtherProceedings of the 1998 IEEE International SOI Conference
CityStuart, FL, USA
Period10/5/9810/8/98

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Allen, L. P., Anc, M. J., Jiao, J., Guss, B., Seraphin, S., Liu, S. T., & Jenkins, W. (1998). Buried oxide densification for low power, low voltage CMOS applications. In Anon (Ed.), IEEE International SOI Conference (pp. 39-40). IEEE.