Abstract
As feature size goes below 70 nm, process variation introduced device mismatch may cause over 40% performance variations and circuit failures especially for analog/mixed-signal designs. The location dependent correlations among devices and the large number of devices in some practical designs make it difficult to predict performance corners accurately and efficiently. This paper aims to provide an overview of possible methodologies and approaches that model and analyze device mismatch. In particular, the paper describes a new finite point device modeling technique that can speed up the analysis procedure, a new parametric reduction method and a novel Chebyshev Affine Arithmetic (CAA) based performance bound estimation approach.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 37-44 |
| Number of pages | 8 |
| Journal | IEEE Circuits and Systems Magazine |
| Volume | 8 |
| Issue number | 4 |
| DOIs | |
| State | Published - Dec 2008 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Science Applications
Cite this
Capturing device mismatch in analog and mixed-signal designs. / Wang, Meiling; Cao, Yu; Chen, Min; Sun, Jin; Mitev, Alex.
In: IEEE Circuits and Systems Magazine, Vol. 8, No. 4, 12.2008, p. 37-44.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Capturing device mismatch in analog and mixed-signal designs
AU - Wang, Meiling
AU - Cao, Yu
AU - Chen, Min
AU - Sun, Jin
AU - Mitev, Alex
PY - 2008/12
Y1 - 2008/12
N2 - As feature size goes below 70 nm, process variation introduced device mismatch may cause over 40% performance variations and circuit failures especially for analog/mixed-signal designs. The location dependent correlations among devices and the large number of devices in some practical designs make it difficult to predict performance corners accurately and efficiently. This paper aims to provide an overview of possible methodologies and approaches that model and analyze device mismatch. In particular, the paper describes a new finite point device modeling technique that can speed up the analysis procedure, a new parametric reduction method and a novel Chebyshev Affine Arithmetic (CAA) based performance bound estimation approach.
AB - As feature size goes below 70 nm, process variation introduced device mismatch may cause over 40% performance variations and circuit failures especially for analog/mixed-signal designs. The location dependent correlations among devices and the large number of devices in some practical designs make it difficult to predict performance corners accurately and efficiently. This paper aims to provide an overview of possible methodologies and approaches that model and analyze device mismatch. In particular, the paper describes a new finite point device modeling technique that can speed up the analysis procedure, a new parametric reduction method and a novel Chebyshev Affine Arithmetic (CAA) based performance bound estimation approach.
UR - http://www.scopus.com/inward/record.url?scp=57649123316&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=57649123316&partnerID=8YFLogxK
U2 - 10.1109/MCAS.2008.930154
DO - 10.1109/MCAS.2008.930154
M3 - Article
AN - SCOPUS:57649123316
VL - 8
SP - 37
EP - 44
JO - IEEE Circuits and Systems Magazine
JF - IEEE Circuits and Systems Magazine
SN - 1531-636X
IS - 4
ER -