Check-hybrid GLDPC codes: Systematic elimination of trapping sets and guaranteed error correction capability

Vida Ravanmehr, Mehrdad Khatami, David Declercq, Bane Vasic

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

In this paper, we propose a new approach to construct a class of check-hybrid generalized low-density parity-check (CH-GLDPC) codes, which are free of small trapping sets. The approach is based on converting some selected check nodes involving a trapping set into super checks corresponding to a 2-error-correcting component code. Specifically, we follow 2 main purposes to construct the check-hybrid codes; first, on the basis of the knowledge of trapping sets of an LDPC code, single parity checks are replaced by super checks to disable the trapping sets. We show that by converting specified single check nodes, denoted as critical checks, to super checks in a trapping set, the parallel bit flipping decoder corrects the errors on a trapping set. The second purpose is to minimize the rate loss through finding the minimum number of such critical checks. We also present an algorithm to find critical checks in a trapping set of a column-weight 3 LDPC code of girth 8 and then provide upper bounds on the minimum number of such critical checks such that the decoder corrects all error patterns on elementary trapping sets. Guaranteed error correction capability of the CH-GLDPC codes is also studied. We show that a CH-GLDPC code in which each variable node is connected to 2 super checks corresponding to a 2-error-correcting component code corrects up to 5 errors. The results are also extended to column-weight 4 LDPC codes of girth 6. Finally, we investigate eliminating of trapping sets of a column-weight 3 LDPC code of girth 8 using the Gallager B decoding algorithm.

Original languageEnglish (US)
Pages (from-to)1679-1692
Number of pages14
JournalTransactions on Emerging Telecommunications Technologies
Volume27
Issue number12
DOIs
StatePublished - Dec 1 2016

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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