With the recent advances in chip fabrication and the ever increasing demand for high performance circuits, the conventional peripheral I/O placement techniques fail to meet the stringent requirements of the chip design. As a result, the existing algorithms result in excessive wire length, long critical paths, and computationally expensive and intensive. In this paper we introduce a new area I/O placement technique that co-designs the chip and package. The present algorithm is non-iterative and constructive. It assigns the functional blocks and primary inputs/outputs simultaneously and considers the package imposed constraints during the planning stage. The algorithm progresses in stages. At each stage, the functional blocks are placed on the chip on the fly and grouped together to form clusters. Various criteria like primary input net span and adjacency of clusters are taken into consideration for the placement of functional blocks. Experimental results showed that due to the non-iterative property, the proposed algorithm achieved 10× speedup over the traditional algorithms while obtaining a planning solution with optimal wire length and minimized delay.
- Chip and package co-design
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering