Cluster extraction for hybrid FPGA architecture in computation intensive applications

Ali Akoglu, Aravind R. Dasu, S. Panchanathan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents experimental results on extraction of common tasks or core clusters in Control Data Flow Graphs (CDFGs) of applications, to embed them in Hybrid-FPGA environment. After removing common sub-graphs from the CDFG, remaining computations are then implemented on LUT based reconfigurable area. A new LUT based packing mechanism using live-in live-out variable analysis and scheduling information is introduced as part of routing architecture design methodology [1]. We conducted experiments on MPEG-4, Gnu Scientific, Biochemical and Molecular modeling libraries. Map report based on Spartan 2E architecture was obtained. Results show that partial reconfiguration with the use of computation cores embedded in a sea of LUTs offer the potential for massive savings in gate density and switching requirements by eliminating the need for unnecessary and redundant sub-circuit pattern configurations.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
EditorsT.P. Plaks
Pages296
Number of pages1
StatePublished - 2004
EventProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 - Las Vegas, NV, United States
Duration: Jun 21 2004Jun 24 2004

Other

OtherProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
CountryUnited States
CityLas Vegas, NV
Period6/21/046/24/04

Fingerprint

Data flow graphs
Field programmable gate arrays (FPGA)
Molecular modeling
Scheduling
Networks (circuits)
Experiments

Keywords

  • Common subgraph
  • Hybrid fpga
  • Packing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Akoglu, A., Dasu, A. R., & Panchanathan, S. (2004). Cluster extraction for hybrid FPGA architecture in computation intensive applications. In T. P. Plaks (Ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 (pp. 296)

Cluster extraction for hybrid FPGA architecture in computation intensive applications. / Akoglu, Ali; Dasu, Aravind R.; Panchanathan, S.

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. ed. / T.P. Plaks. 2004. p. 296.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Akoglu, A, Dasu, AR & Panchanathan, S 2004, Cluster extraction for hybrid FPGA architecture in computation intensive applications. in TP Plaks (ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. pp. 296, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, Las Vegas, NV, United States, 6/21/04.
Akoglu A, Dasu AR, Panchanathan S. Cluster extraction for hybrid FPGA architecture in computation intensive applications. In Plaks TP, editor, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. 2004. p. 296
Akoglu, Ali ; Dasu, Aravind R. ; Panchanathan, S. / Cluster extraction for hybrid FPGA architecture in computation intensive applications. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. editor / T.P. Plaks. 2004. pp. 296
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