Coding for Efficient Caching in Multicore Embedded Systems

We present an information theoretic approach to caching in multicore embedded systems. In contrast to conventional approaches where caches are treated independently, we leverage novel cache placement and coded data delivery algorithms that treat the caches holistically, and provably reduce the communication overhead resulting from main memory accesses. The proposed approach intelligently places data across the processors' caches such that in the event of cache misses, the main memory can opportunistically send coded data blocks that are simultaneously useful to multiple processors. Using architectural simulations, we demonstrate that the coded caching approach significantly reduces the communication overhead, thus reducing the overall memory access energy and latency, while imposing minimal overheads. In a quad-core embedded system, compared to conventional caching schemes, the coded caching approach reduced the access energy and latency by an average of 36% and 16%, respectively.