Computer aided design system for VLSI interconnections

Jerzy W Rozenblit, J. L. Prince, O. A. Palusinski, T. D. Whipple

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A simulation environment for prediction of electrical characteristics of integrated circuit packaging structures is described. The simulation shell, Packaging Design Support Environment (PDSE), integrates tools for modeling and simulation of electrical characteristics in VLSI packages. It also provides facilities for supporting design of VLSI packages. Two simulation tools model inductance and capacitance for multiconductor, multidielectric, two-dimensional structures with lossy dielectrics. Another accepts the L and C matrices and computes pulse response characteristics of uniform multiple, coupled, lossless transmission lines which are terminated at discrete points with R, L, and C elements. The design process in PDSE proceeds in three major phases: modeling, simulation, and evaluation. These processes are interactive and allow the designer to refine a design model, modify simulation experiments, and apply various evaluation processes.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Editors Anon
PublisherPubl by IEEE
Pages237-241
Number of pages5
StatePublished - 1989
EventProceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA
Duration: Oct 2 1989Oct 4 1989

Other

OtherProceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors
CityCambridge, MA, USA
Period10/2/8910/4/89

Fingerprint

Computer aided design
Packaging
Inductance
Integrated circuits
Electric lines
Capacitance
Computer simulation
Experiments

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Engineering(all)

Cite this

Rozenblit, J. W., Prince, J. L., Palusinski, O. A., & Whipple, T. D. (1989). Computer aided design system for VLSI interconnections. In Anon (Ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 237-241). Publ by IEEE.

Computer aided design system for VLSI interconnections. / Rozenblit, Jerzy W; Prince, J. L.; Palusinski, O. A.; Whipple, T. D.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. ed. / Anon. Publ by IEEE, 1989. p. 237-241.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rozenblit, JW, Prince, JL, Palusinski, OA & Whipple, TD 1989, Computer aided design system for VLSI interconnections. in Anon (ed.), Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, pp. 237-241, Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors, Cambridge, MA, USA, 10/2/89.
Rozenblit JW, Prince JL, Palusinski OA, Whipple TD. Computer aided design system for VLSI interconnections. In Anon, editor, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE. 1989. p. 237-241
Rozenblit, Jerzy W ; Prince, J. L. ; Palusinski, O. A. ; Whipple, T. D. / Computer aided design system for VLSI interconnections. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. editor / Anon. Publ by IEEE, 1989. pp. 237-241
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