Configuration locking and schedulability estimation for reduced reconfiguration overheads of reconfigurable systems

Rahul Kalra, Roman L Lysecky

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

Dynamically reconfigurable field-programmable gate arrays (FPGAs) hold the promise of providing a virtual hardware resource in which hardware circuits can be dynamically scheduled onto the available FPGA resources. However, reconfiguring an FPGA can incur significant performance and energy overheads. This paper analyzes the relationship between several hardware task scheduling algorithms and their impact on the number of reconfigurations required to execute a set of hardware tasks. In addition, three new hardware scheduling algorithms, specifically designed to reduce the number of required reconfigurations, are presented and analyzed. By selectively locking configurations within the reconfigurable tiles of an FPGA, significant reductions in the number of required reconfiguration can be achieved.

Original languageEnglish (US)
Article number5067004
Pages (from-to)671-674
Number of pages4
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume18
Issue number4
DOIs
StatePublished - Apr 2010

Fingerprint

Field programmable gate arrays (FPGA)
Hardware
Scheduling algorithms
Tile
Networks (circuits)

Keywords

  • Dynamic reconfiguration
  • Field-programmable gate arrays (FPGAs)
  • Hardware task scheduling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

Cite this

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