Conjoining soft-core FPGA processors

David Sheldon, Rakesh Kumar, Frank Vahid, Dean Tullsen, Roman L Lysecky

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

Soft-core programmable processors on field-programmable gate arrays (FPGAs) can be custom synthesized to instantiate only those hardware units, such as multipliers and floating-point units, that an application requires to meet performance demands, thus minimizing soft-core size on the FPGA. Conjoining processors, meaning to share hardware units among two or more processors, can further reduce soft-core size, leaving more resources for other circuits such as custom coprocessors. Using Xilinx MicroBlaze coprocessors and standard embedded system benchmarks, we show that conjoining two processors can provide 16% processor size reductions on average, with less than 1% cycle count overhead. We introduce an efficient dynamic-programming-based exploration method to find the best custom instantiation of hardware units, considering both standalone and conjoined options, for soft-core processors.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Pages694-701
Number of pages8
DOIs
StatePublished - 2006
Event2006 International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States
Duration: Nov 5 2006Nov 9 2006

Other

Other2006 International Conference on Computer-Aided Design, ICCAD
CountryUnited States
CitySan Jose, CA
Period11/5/0611/9/06

Fingerprint

Parallel processing systems
Field programmable gate arrays (FPGA)
Hardware
Dynamic programming
Embedded systems
Networks (circuits)
Coprocessor

Keywords

  • Conjoined processors
  • Customization
  • FPGAs
  • Parameterized platforms
  • Soft-core processors
  • Tuning

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Sheldon, D., Kumar, R., Vahid, F., Tullsen, D., & Lysecky, R. L. (2006). Conjoining soft-core FPGA processors. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD (pp. 694-701). [4110254] https://doi.org/10.1109/ICCAD.2006.320015

Conjoining soft-core FPGA processors. / Sheldon, David; Kumar, Rakesh; Vahid, Frank; Tullsen, Dean; Lysecky, Roman L.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2006. p. 694-701 4110254.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sheldon, D, Kumar, R, Vahid, F, Tullsen, D & Lysecky, RL 2006, Conjoining soft-core FPGA processors. in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD., 4110254, pp. 694-701, 2006 International Conference on Computer-Aided Design, ICCAD, San Jose, CA, United States, 11/5/06. https://doi.org/10.1109/ICCAD.2006.320015
Sheldon D, Kumar R, Vahid F, Tullsen D, Lysecky RL. Conjoining soft-core FPGA processors. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2006. p. 694-701. 4110254 https://doi.org/10.1109/ICCAD.2006.320015
Sheldon, David ; Kumar, Rakesh ; Vahid, Frank ; Tullsen, Dean ; Lysecky, Roman L. / Conjoining soft-core FPGA processors. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. 2006. pp. 694-701
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